HT1621
RAM Mapping 324 LCD Controller for I/O MCU
Selection Table
HT162X
HT1620
HT1621
HT1622
HT16220
HT1623
HT1625
HT1626
COM
4
4
8
8
8
8
16
SEG
32
32
32
32
48
64
48
Built-in Osc.
Crystal Osc.
Rev. 1.30
1
August 6, 2003
Features
Operating voltage: 2.4V~5.2V
Built-in 256kHz RC oscillator
External 32.768kHz crystal or 256kHz frequency
source input
Selection of 1/2 or 1/3 bias, and selection of 1/2 or
1/3 or 1/4 duty LCD applications
Internal time base frequency sources
Two selectable buzzer frequencies (2kHz/4kHz)
Power down command reduces power consumption
Built-in time base generator and WDT
Time base or WDT overflow output
8 kinds of time base/WDT clock sources
32
4 LCD driver
Built-in 32
4 bit display RAM
3-wire serial interface
Internal LCD driving frequency source
Software configuration feature
Data mode and command mode instructions
R/W address auto increment
Three data accessing modes
VLCD pin for adjusting LCD operating voltage
HT1621: 48-pin SSOP package
HT1621B: 48-pin DIP/SSOP/LQFP package
HT1621D: 28-pin SKDIP package
HT1621G: Gold bumped chip
General Description
The HT1621 is a 128 pattern (32
4), memory mapping,
and multi-function LCD driver. The S/W configuration
feature of the HT1621 makes it suitable for multiple LCD
applications including LCD modules and display sub-
systems. Only three or four lines are required for the in-
terface between the host controller and the HT1621.
The HT1621 contains a power down command to re-
duce power consumption.
Block Diagram
Note:
CS: Chip selection
BZ, BZ: Tone outputs
WR, RD, DATA: Serial interface
COM0~COM3, SEG0~SEG31: LCD outputs
IRQ: Time base or WDT overflow output
Pin Assignment
HT1621
Rev. 1.30
2
August 6, 2003
W a t c h d o g T i m e r
a n d
T i m e B a s e G e n e r a t o r
D i s p l a y R A M
L C D D r i v e r /
B i a s C i r c u i t
C o n t r o l
a n d
T i m i n g
C i r c u i t
D A T A
W R
O S C O
O S C I
C S
R D
C O M 0
C O M 3
S E G 0
S E G 3 1
T o n e F r e q u e n c y
G e n e r a t o r
B Z
B Z
I R Q
V S S
V D D
V L C D
S E G 7
S E G 6
S E G 5
S E G 4
S E G 3
S E G 2
S E G 1
S E G 0
C S
R D
W R
D A T A
V S S
O S C O
N C
O S C I
V D D / V L C D
I R Q
B Z
B Z
C O M 0
C O M 1
C O M 2
C O M 3
S E G 8
S E G 9
S E G 1 0
S E G 1 1
S E G 1 2
S E G 1 3
S E G 1 4
S E G 1 5
S E G 1 6
S E G 1 7
S E G 1 8
S E G 1 9
S E G 2 0
S E G 2 1
S E G 2 2
S E G 2 3
S E G 2 4
S E G 2 5
S E G 2 6
S E G 2 7
S E G 2 8
S E G 2 9
S E G 3 0
S E G 3 1
H T 1 6 2 1
4 8 S S O P - A
S E G 7
S E G 6
S E G 5
S E G 4
S E G 3
S E G 2
S E G 1
S E G 0
C S
R D
W R
D A T A
V S S
O S C O
O S C I
V L C D
V D D
I R Q
B Z
B Z
C O M 0
C O M 1
C O M 2
C O M 3
S E G 8
S E G 9
S E G 1 0
S E G 1 1
S E G 1 2
S E G 1 3
S E G 1 4
S E G 1 5
S E G 1 6
S E G 1 7
S E G 1 8
S E G 1 9
S E G 2 0
S E G 2 1
S E G 2 2
S E G 2 3
S E G 2 4
S E G 2 5
S E G 2 6
S E G 2 7
S E G 2 8
S E G 2 9
S E G 3 0
S E G 3 1
H T 1 6 2 1 B
4 8 S S O P - A / D I P - A
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
S E G 5
S E G 3
S E G 1
C S
R D
W R
D A T A
V S S
V L C D
V D D
I R Q
B Z
C O M 0
C O M 1
H T 1 6 2 1 D
2 8 S K D I P - A
S E G 7
S E G 9
S E G 1 1
S E G 1 3
S E G 1 5
S E G 1 7
S E G 1 9
S E G 2 1
S E G 2 3
S E G 2 5
S E G 2 7
S E G 2 9
S E G 3 1
C O M 2
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
Pad Assignment
Chip size: 127
131 (mil)
2
Bump height: 18
mm 3mm
Min. Bump spacing: 72.36
mm
Bump size: 96.042
96.042mm
2
* The IC substrate should be connected to VDD in the PCB layout artwork.
HT1621
Rev. 1.30
3
August 6, 2003
C S
R D
W R
D A T A
V S S
O S C O
O S C I
V L C D
V D D
I R Q
B Z
B Z
S E G 1 2
S E G 1 3
S E G 1 4
S E G 1 5
S E G 1 6
S E G 1 7
S E G 1 8
S G E 1 9
S E G 2 0
S E G 2 1
S E G 2 2
S E G 2 3
S
E
G
2
4
S
E
G
2
5
S
E
G
2
6
S
E
G
2
8
S
E
G
2
7
S
E
G
2
9
S
E
G
3
0
S
E
G
3
1
C
O
M
3
C
O
M
2
C
O
M
1
C
O
M
0
S
E
G
1
1
S
E
G
1
0
S
E
G
9
S
E
G
8
S
E
G
7
S
E
G
6
S
E
G
5
S
E
G
4
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0
2 1 2 2 2 3 2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0
4 8
4 1
4 2
4 3
4 4
4 5
4 6
4 7
H T 1 6 2 1 B
4 8 L Q F P - A
I
R
Q
B
Z
C
S
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4 1 5
1 6 1 7 1 8
1 9
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
( 0 , 0 )
R D
W R
D A T A
V S S
O S C O
O S C I
V L C D
V D D
B
Z
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
S
E
G
3
1
S
E
G
3
0
S
E
G
2
9
S E G 2 8
S E G 2 7
S E G 2 6
S E G 2 5
S E G 2 4
S E G 2 3
S E G 2 2
S E G 2 1
S E G 2 0
S E G 1 9
S E G 1 8
S E G 1 7
S E G 1 6
S
E
G
1
5
S
E
G
1
4
S
E
G
1
3
S
E
G
1
2
S
E
G
1
1
S
E
G
1
0
S
E
G
9
S
E
G
8
S
E
G
7
S
E
G
6
S
E
G
5
S
E
G
4
S
E
G
3
S
E
G
2
S
E
G
1
S
E
G
0
Pad Coordinates
Unit: mil
Pad No.
X
Y
Pad No.
X
Y
1
-55.04
59.46
25
58.14
-25.29
2
-58.52
22.18
26
58.14
-18.66
3
-58.52
15.56
27
58.14
-11.94
4
-58.52
5.36
28
58.14
-5.31
5
-58.52
-4.51
29
58.14
1.32
6
-58.52
-11.14
30
58.14
7.95
7
-58.52
-34.76
31
58.14
14.58
8
-58.52
-41.90
32
58.14
21.21
9
-58.52
-49.13
33
55.55
59.46
10
-58.52
-59.08
34
48.92
59.46
11
-44.07
-59.08
35
42.29
59.46
12
-31.58
-59.08
36
35.66
59.46
13
-20.70
-59.08
37
29.03
59.46
14
-13.98
-59.08
38
22.40
59.46
15
-7.05
-59.08
39
15.77
59.46
16
-0.34
-59.08
40
9.14
59.46
17
6.33
-59.08
41
2.42
59.46
18
12.96
-59.08
42
-4.21
59.46
19
19.59
-59.08
43
-10.84
59.46
20
58.14
-58.44
44
-17.47
59.46
21
58.14
-51.81
45
-24.10
59.46
22
58.14
-45.18
46
-30.73
59.46
23
58.14
-38.55
47
-38.17
59.46
24
58.14
-31.92
48
-45.39
59.46
Pad Description
Pad No.
Pad Name
I/O
Function
1
CS
I
Chip selection input with pull-high resistor
When the CS is logic high, the data and command read from or written to
the HT1621 are disabled. The serial interface circuit is also reset. But if CS
is at logic low level and is input to the CS pad, the data and command trans-
mission between the host controller and the HT1621 are all enabled.
2
RD
I
READ clock input with pull-high resistor
Data in the RAM of the HT1621 are clocked out on the falling edge of the RD
signal. The clocked out data will appear on the DATA line. The host control-
ler can use the next rising edge to latch the clocked out data.
3
WR
I
WRITE clock input with pull-high resistor
Data on the DATA line are latched into the HT1621 on the rising edge of the
WR signal.
4
DATA
I/O
Serial data input/output with pull-high resistor
5
VSS
Negative power supply, ground
7
OSCI
I
The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to
generate a system clock. If the system clock comes from an external clock
source, the external clock source should be connected to the OSCI pad. But
if an on-chip RC oscillator is selected instead, the OSCI and OSCO pads
can be left open.
6
OSCO
O
8
VLCD
I
LCD power input
9
VDD
Positive power supply
10
IRQ
O
Time base or WDT overflow flag, NMOS open drain output
11, 12
BZ, BZ
O
2kHz or 4kHz tone frequency output pair
13~16
COM0~COM3
O
LCD common outputs
48~17
SEG0~SEG31
O
LCD segment outputs
HT1621
Rev. 1.30
4
August 6, 2003
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V to V
SS
+5.5V
Storage Temperature ............................
-50
o
C to 125
o
C
Input Voltage..............................V
SS
-0.3V to V
DD
+0.3V
Operating Temperature...........................
-25
o
C to 75
o
C
Note: These are stress ratings only. Stresses exceeding the range specified under
Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
V
DD
Operating Voltage
2.4
5.2
V
I
DD1
Operating Current
3V
No load/LCD ON
On-chip RC oscillator
150
300
mA
5V
300
600
mA
I
DD2
Operating Current
3V
No load/LCD ON
Crystal oscillator
60
120
mA
5V
120
240
mA
I
DD3
Operating Current
3V
No load/LCD ON
External clock source
100
200
mA
5V
200
400
mA
I
STB
Standby Current
3V
No load, Power down mode
0.1
5
mA
5V
0.3
10
mA
V
IL
Input Low Voltage
3V
DATA, WR, CS, RD
0
0.6
V
5V
0
1.0
V
V
IH
Input High Voltage
3V
DATA, WR, CS, RD
2.4
3.0
V
5V
4.0
5.0
V
I
OL1
DATA, BZ, BZ, IRQ
3V
V
OL
=0.3V
0.5
1.2
mA
5V
V
OL
=0.5V
1.3
2.6
mA
I
OH1
DATA, BZ, BZ
3V
V
OH
=2.7V
-0.4
-0.8
mA
5V
V
OH
=4.5V
-0.9
-1.8
mA
I
OL2
LCD Common Sink Current
3V
V
OL
=0.3V
80
150
mA
5V
V
OL
=0.5V
150
250
mA
I
OH2
LCD Common Source Current
3V
V
OH
=2.7V
-80
-120
mA
5V
V
OH
=4.5V
-120
-200
mA
I
OL3
LCD Segment Sink Current
3V
V
OL
=0.3V
60
120
mA
5V
V
OL
=0.5V
120
200
mA
I
OH3
LCD Segment Source Current
3V
V
OH
=2.7V
-40
-70
mA
5V
V
OH
=4.5V
-70
-100
mA
R
PH
Pull-high Resistor
3V
DATA, WR, CS, RD
40
80
150
k
W
5V
30
60
100
k
W
HT1621
Rev. 1.30
5
August 6, 2003
A.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
f
SYS1
System Clock
On-chip RC oscillator
256
kHz
f
SYS2
System Clock
Crystal oscillator
32.768
kHz
f
SYS3
System Clock
External clock source
256
kHz
f
LCD
LCD Clock
On-chip RC oscillator
f
SYS1
/1024
Hz
Crystal oscillator
f
SYS2
/128
Hz
External clock source
f
SYS3
/1024
Hz
t
COM
LCD Common Period
n: Number of COM
n/f
LCD
s
f
CLK1
Serial Data Clock (WR pin)
3V
Duty cycle 50%
150
kHz
5V
300
kHz
f
CLK2
Serial Data Clock (RD pin)
3V
Duty cycle 50%
75
kHz
5V
150
kHz
f
TONE
Tone Frequency
On-chip RC oscillator
2.0 or 4.0
kHz
t
CS
Serial Interface Reset Pulse
Width (Figure 3)
CS
250
ns
t
CLK
WR, RD Input Pulse Width
(Figure 1)
3V
Write mode
3.34
ms
Read mode
6.67
5V
Write mode
1.67
ms
Read mode
3.34
t
r
, t
f
Rise/Fall Time Serial Data
Clock Width (Figure 1)
120
ns
t
su
Setup Time for DATA to WR,
RD Clock Width (Figure 2)
120
ns
t
h
Hold Time for DATA to WR, RD
Clock Width (Figure 2)
120
ns
t
su1
Setup Time for CS to WR, RD
Clock Width (Figure 3)
100
ns
t
h1
Hold Time for CS to WR, RD
Clock Width (Figure 3)
100
ns
HT1621
Rev. 1.30
6
August 6, 2003
C S
G N D
5 0 %
5 0 %
F i r s t C l o c k
L a s t C l o c k
G N D
W R , R D
C l o c k
t
S U 1
t
h 1
t
C S
V
D D
V
D D
Figure 3
9 0 %
5 0 %
1 0 %
G N D
W R , R D
C l o c k
t
f
t
r
t
C L K
t
C L K
V
D D
Figure 1
5 0 %
V a l i d D a t a
5 0 %
D B
W R , R D
C l o c k
G N D
G N D
t
h
t
S U
V
D D
V
D D
Figure 2
HT1621
Rev. 1.30
7
August 6, 2003
Functional Description
Display Memory
- RAM
The static display memory (RAM) is organized into 32
4
bits and stores the displayed data. The contents of the
RAM are directly mapped to the contents of the LCD
driver. Data in the RAM can be accessed by the READ,
WRITE, and READ-MODIFY-WRITE commands. The
following is a mapping from the RAM to the LCD pattern:
System Oscillator
The HT1621 system clock is used to generate the time
base/Watchdog Timer (WDT) clock frequency, LCD
driving clock, and tone frequency. The source of the
clock may be from an on-chip RC oscillator (256kHz), a
crystal oscillator (32.768kHz), or an external 256kHz
clock by the S/W setting. The configuration of the sys-
tem oscillator is as shown. After the SYS DIS command
is executed, the system clock will stop and the LCD bias
generator will turn off. That command is, however, avail-
able only for the on-chip RC oscillator or for the crystal
oscillator. Once the system clock stops, the LCD display
will become blank, and the time base/WDT lose its func-
tion as well.
The LCD OFF command is used to turn the LCD bias
generator off. After the LCD bias generator switches off
by issuing the LCD OFF command, using the SYS DIS
command reduces power consumption, serving as a
system power down command. But if the external clock
source is chosen as the system clock, using the SYS
DIS command can neither turn the oscillator off nor
carry out the power down mode. The crystal oscillator
option can be applied to connect an external frequency
source of 32kHz to the OSCI pin. In this case, the sys-
tem fails to enter the power down mode, similar to the
case in the external 256kHz clock source operation. At
the initial system power on, the HT1621 is at the SYS
DIS state.
Time Base and Watchdog Timer (WDT)
The time base generator is comprised by an 8-stage
count-up ripple counter and is designed to generate an
accurate time base. The watch dog timer (WDT), on the
other hand, is composed of an 8-stage time base gener-
ator along with a 2-stage count-up counter, and is de-
signed to break the host controller or other subsystems
from abnormal states such as unknown or unwanted
jump, execution errors, etc. The WDT time-out will result
in the setting of an internal WDT time-out flag. The out-
puts of the time base generator and of the WDT time-out
flag can be connected to the IRQ output by a command
option. There are totally eight frequency sources avail-
able for the time base generator and the WDT clock.
The frequency is calculated by the following equation.
f
WDT
=
32kHz
2
n
where the value of n ranges from 0 to 7 by command op-
tions. The 32kHz in the above equation indicates that
the source of the system frequency is derived from a
crystal oscillator of 32.768kHz, an on-chip oscillator
(256kHz), or an external frequency of 256kHz.
If an on-chip oscillator (256kHz) or an external 256kHz
frequency is chosen as the source of the system fre-
quency, the frequency source is by default prescaled to
32kHz by a 3-stage prescaler. Employing both the time
base generator and the WDT related commands, one
should be careful since the time base generator and
WDT share the same 8-stage counter. For example, in-
voking the WDT DIS command disables the time base
generator whereas executing the WDT EN command
S E G 0
S E G 1
S E G 2
S E G 3
S E G 3 1
C O M 0
C O M 1
C O M 2
C O M 3
D 3
D 2
D 1
D 0
D a t a
A d d r
3 1
0
1
2
3
A d d r e s s 6 b i t s
( A 5 , A 4 , . . . , A 0 )
D a t a 4 b i t s
( D 3 , D 2 , D 1 , D 0 )
RAM Mapping
1 / 8
O S C I
O S C O
C r y s t a l O s c i l l a t o r
3 2 7 6 8 H z
E x t e r n a l C l o c k S o u r c e
2 5 6 k H z
O n - c h i p R C O s c i l l a t o r
2 5 6 k H z
S y s t e m
C l o c k
System Oscillator Configuration
HT1621
Rev. 1.30
8
August 6, 2003
not only enables the time base generator but activates
the WDT time-out flag output (connect the WDT
time-out flag to the IRQ pin). After the TIMER EN com-
mand is transferred, the WDT is disconnected from the
IRQ pin, and the output of the time base generator is con-
nected to the IRQ pin. The WDT can be cleared by execut-
ing the CLR WDT command, and the contents of the time
base generator is cleared by executing the CLR WDT or
the CLR TIMER command. The CLR WDT or the CLR
TIMER command should be executed prior to the WDT
EN or the TIMER EN command respectively. Before ex-
ecuting the IRQ EN command the CLR WDT or CLR
TIMER command should be executed first. The CLR
TIMER command has to be executed before switching
from the WDT mode to the time base mode. Once the
WDT time-out occurs, the IRQ pin will stay at a logic low
level until the CLR WDT or the IRQ DIS command is is-
sued. After the IRQ output is disabled the IRQ pin will re-
main at the floating state. The IRQ output can be
enabled or disabled by executing the IRQ EN or the IRQ
DIS command, respectively. The IRQ EN makes the
output of the time base generator or of the WDT time-out
flag appear on the IRQ pin. The configuration of the time
base generator along with the WDT are as shown. In the
case of on-chip RC oscillator or crystal oscillator, the
power down mode can reduce power consumption
since the oscillator can be turned on or off by the corre-
sponding system commands. At the power down mode
the time base/WDT loses all its functions.
On the other hand, if an external clock is selected as the
source of system frequency the SYS DIS command
turns out invalid and the power down mode fails to be
carried out. That is, after the external clock source is se-
lected, the HT1621 will continue working until system
power fails or the external clock source is removed. Af-
ter the system power on, the IRQ will be disabled.
Tone Output
A simple tone generator is implemented in the HT1621.
The tone generator can output a pair of differential driv-
ing signals on the BZ and BZ, which are used to gener-
ate a single tone. By executing the TONE4K and
TONE2K commands there are two tone frequency out-
puts selectable. The TONE4K and TONE2K commands
set the tone frequency to 4kHz and 2kHz, respectively.
The tone output can be turned on or off by invoking the
TONE ON or the TONE OFF command. The tone out-
puts, namely BZ and BZ, are a pair of differential driving
outputs used to drive a piezo buzzer. Once the system is
disabled or the tone output is inhibited, the BZ and the
BZ outputs will remain at low level.
LCD Driver
The HT1621 is a 128 (32
4) pattern LCD driver. It can be
configured as 1/2 or 1/3 bias and 2 or 3 or 4 commons of
LCD driver by the S/W configuration. This feature
makes the HT1621 suitable for multiply LCD applica-
tions. The LCD driving clock is derived from the system
clock. The value of the driving clock is always 256Hz even
when it is at a 32.768kHz crystal oscillator frequency, an
on-chip RC oscillator frequency, or an external fre-
quency. The LCD corresponding commands are sum-
marized in the table.
The bold form of 1 0 0, namely 1 0 0, indicates the com-
mand mode ID. If successive commands have been is-
sued, the command mode ID except for the first
command, will be omitted. The LCD OFF command
turns the LCD display off by disabling the LCD bias gen-
T I M E R E N / D I S
W D T E N / D I S
V
D D
I R Q
I R Q E N / D I S
D
C K
Q
R
C L R W D T
S y s t e m C l o c k
f = 3 2 k H z
/ 2 5 6
/ 4
W D T
T i m e r / W D T
C l o c k S o u r c e s
/ 2
n
n = 0 ~ 7
Timer and WDT Configurations
Name
Command Code
Function
LCD OFF
1 0 0 0 0 0 0 0 0 1 0 X
Turn off LCD outputs
LCD ON
1 0 0 0 0 0 0 0 0 1 1 X
Turn on LCD outputs
BIAS & COM
1 0 0 0 0 1 0 a b X c X
c=0: 1/2 bias option
c=1: 1/3 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
Timing Diagrams
READ Mode (Command Code : 1 1 0)
HT1621
Rev. 1.30
9
August 6, 2003
erator. The LCD ON command, on the other hand, turns
the LCD display on by enabling the LCD bias generator.
The BIAS and COM are the LCD panel related com-
mands. Using the LCD related commands, the HT1621
can be compatible with most types of LCD panels.
Command Format
The HT1621 can be configured by the S/W setting. There
are two mode commands to configure the HT1621 re-
sources and to transfer the LCD display data. The configu-
ration mode of the HT1621 is called command mode, and
its command mode ID is 1 0 0. The command mode con-
sists of a system configuration command, a system
frequency selection command, a LCD configuration com-
mand, a tone frequency selection command, a timer/WDT
setting command, and an operating command. The data
mode, on the other hand, includes READ, WRITE, and
READ-MODIFY-WRITE operations. The following are the
data mode IDs and the command mode ID:
Operation
Mode
ID
Read
Data
1 1 0
Write
Data
1 0 1
Read-Modify-Write
Data
1 0 1
Command
Command
1 0 0
The mode command should be issued before the data
or command is transferred. If successive commands
have been issued, the command mode ID, namely 1 0 0,
can be omitted. While the system is operating in the
non-successive command or the non-successive ad-
dress data mode, the CS pin should be set to
1 and the
previous operation mode will be reset also. Once the CS
pin returns to
0 a new operation mode ID should be is-
sued first.
Interfacing
Only four lines are required to interface with the
HT1621. The CS line is used to initialize the serial inter-
face circuit and to terminate the communication between
the host controller and the HT1621. If the CS pin is set to 1,
the data and command issued between the host controller
and the HT1621 are first disabled and then initialized. Be-
fore issuing a mode command or mode switching, a high
level pulse is required to initialize the serial interface of the
HT1621. The DATA line is the serial data input/output line.
Data to be read or written or commands to be written have
to be passed through the DATA line. The RD line is the
READ clock input. Data in the RAM are clocked out on the
falling edge of the RD signal, and the clocked out data will
then appear on the DATA line. It is recommended that the
host controller read in correct data during the interval be-
tween the rising edge and the next falling edge of the RD
signal. The WR line is the WRITE clock input. The data,
address, and command on the DATA line are all clocked
into the HT1621 on the rising edge of the WR signal. There
is an optional IRQ line to be used as an interface between
the host controller and the HT1621. The IRQ pin can be
selected as a timer output or a WDT overflow flag output
by the S/W setting. The host controller can perform the
time base or the WDT function by being connected with
the IRQ pin of the HT1621.
R D
D A T A
W R
1
1
0 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s 1 ( M A 1 )
D a t a ( M A 2 )
1
1
0 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
D a t a ( M A 1 )
M e m o r y A d d r e s s 2 ( M A 2 )
C S
READ Mode (Successive Address Reading)
WRITE Mode (Command Code : 1 0 1)
WRITE Mode (Successive Address Writing)
Read-Modify-Write Mode (Command Code : 1 0 1)
HT1621
Rev. 1.30
10
August 6, 2003
R D
D A T A
C S
W R
1
1
0 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s ( M A ) D a t a ( M A )
D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0
D a t a ( M A + 1 ) D a t a ( M A + 2 ) D a t a ( M A + 3 )
D A T A
C S
W R
1
0
1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s 1 ( M A 1 ) D a t a ( M A 1 )
1
0
1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s 2 ( M A 2 ) D a t a ( M A 2 )
D A T A
C S
W R
1
0
1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s ( M A ) D a t a ( M A )
D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0
D a t a ( M A + 1 ) D a t a ( M A + 2 ) D a t a ( M A + 3 )
D A T A
C S
W R
1
0
1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s 1 ( M A 1 ) D a t a ( M A 1 )
A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s 2 ( M A 2 ) D a t a ( M A 2 )
1
0
1
R D
D 0 D 1 D 2 D 3
D a t a ( M A 1 )
Read-Modify-Write Mode (Successive Address Accessing)
Command Mode (Command Code : 1 0 0)
Mode (Data And Command Mode)
Note:
It is recommended that the host controller should read in the data from the DATA line between the rising edge
of the RD line and the falling edge of the next RD line.
HT1621
Rev. 1.30
11
August 6, 2003
D A T A
C S
W R
1
0
1 A 5 A 4 A 3 A 2 A 1 A 0 D 0 D 1 D 2 D 3
M e m o r y A d d r e s s ( M A ) D a t a ( M A )
D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0 D 1 D 2 D 3 D 0
D a t a ( M A )
D a t a ( M A + 1 ) D a t a ( M A + 1 )
R D
D 1 D 2 D 3 D 0
D a t a ( M A + 2 )
D A T A
C S
W R
1
0
0 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0
C o m m a n d 1
C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0
C o m m a n d i
C o m m a n d . . .
C o m m a n d
o r
D a t a M o d e
R D
D A T A
C S
W R
A d d r e s s & D a t a
C o m m a n d
o r
D a t a M o d e
A d d r e s s a n d D a t a
C o m m a n d
o r
D a t a M o d e
A d d r e s s a n d D a t a
C o m m a n d
o r
D a t a M o d e
Application Circuits
Host Controller with an HT1621 Display System
Note:
The connection of IRQ and RD pin can be selected depending on the requirement of the MCU.
The voltage applied to V
LCD
pin must be lower than V
DD
.
Adjust VR to fit LCD display, at V
DD
=5V, V
LCD
=4V, VR=15k
W20%.
Adjust R (external pull-high resistance) to fit user's time base clock.
Command Summary
HT1621
Rev. 1.30
12
August 6, 2003
I R Q
D A T A
*
O n - c h i p O S C
O S C I
O S C O
C l o c k O u t
E x t e r n a l C o l c k 1
E x t e r n a l C o l c k 2
C S
R D
W R
C r y s t a l
3 2 7 6 8 H z
H T 1 6 2 1 B
L C D P a n e l
B Z
B Z
C O M 0 ~ C O M 3
S E G 0 ~ S E G 3 1
P i e z o
1 / 2 o r 1 / 3 B i a s ; 1 / 2 , 1 / 3 o r 1 / 4 D u t y
R
*
V R
*
V D D
V L C D
M C U
Name
ID
Command Code
D/C
Function
Def.
READ
1 1 0
A5A4A3A2A1A0D0D1D2D3
D
Read data from the RAM
WRITE
1 0 1
A5A4A3A2A1A0D0D1D2D3
D
Write data to the RAM
READ-MODIFY-
WRITE
1 0 1
A5A4A3A2A1A0D0D1D2D3
D
READ and WRITE to the RAM
SYS DIS
1 0 0
0000-0000-X
C
Turn off both system oscillator and LCD
bias generator
Yes
SYS EN
1 0 0
0000-0001-X
C
Turn on system oscillator
LCD OFF
1 0 0
0000-0010-X
C
Turn off LCD bias generator
Yes
LCD ON
1 0 0
0000-0011-X
C
Turn on LCD bias generator
TIMER DIS
1 0 0
0000-0100-X
C
Disable time base output
WDT DIS
1 0 0
0000-0101-X
C
Disable WDT time-out flag output
TIMER EN
1 0 0
0000-0110-X
C
Enable time base output
WDT EN
1 0 0
0000-0111-X
C
Enable WDT time-out flag output
TONE OFF
1 0 0
0000-1000-X
C
Turn off tone outputs
Yes
TONE ON
1 0 0
0000-1001-X
C
Turn on tone outputs
CLR TIMER
1 0 0
0000-11XX-X
C
Clear the contents of time base generator
CLR WDT
1 0 0
0000-111X-X
C
Clear the contents of WDT stage
XTAL 32K
1 0 0
0001-01XX-X
C
System clock source, crystal oscillator
HT1621
Rev. 1.30
13
August 6, 2003
Name
ID
Command Code
D/C
Function
Def.
RC 256K
1 0 0
0001-10XX-X
C
System clock source, on-chip RC oscillator
Yes
EXT 256K
1 0 0
0001-11XX-X
C
System clock source, external clock source
BIAS 1/2
1 0 0
0010-abX0-X
C
LCD 1/2 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
BIAS 1/3
1 0 0
0010-abX1-X
C
LCD 1/3 bias option
ab=00: 2 commons option
ab=01: 3 commons option
ab=10: 4 commons option
TONE 4K
1 0 0
010X-XXXX-X
C
Tone frequency, 4kHz
TONE 2K
1 0 0
011X-XXXX-X
C
Tone frequency, 2kHz
IRQ DIS
1 0 0
100X-0XXX-X
C
Disable IRQ output
Yes
IRQ EN
1 0 0
100X-1XXX-X
C
Enable IRQ output
F1
1 0 0
101X-X000-X
C
Time base/WDT clock output:1Hz
The WDT time-out flag after: 4s
F2
1 0 0
101X-X001-X
C
Time base/WDT clock output:2Hz
The WDT time-out flag after: 2s
F4
1 0 0
101X-X010-X
C
Time base/WDT clock output:4Hz
The WDT time-out flag after: 1s
F8
1 0 0
101X-X011-X
C
Time base/WDT clock output:8Hz
The WDT time-out flag after: 1/2s
F16
1 0 0
101X-X100-X
C
Time base/WDT clock output:16Hz
The WDT time-out flag after: 1/4s
F32
1 0 0
101X-X101-X
C
Time base/WDT clock output:32Hz
The WDT time-out flag after: 1/8s
F64
1 0 0
101X-X110-X
C
Time base/WDT clock output:64Hz
The WDT time-out flag after: 1/16s
F128
1 0 0
101X-X111-X
C
Time base/WDT clock output:128Hz
The WDT time-out flag after: 1/32s
Yes
TEST
1 0 0
1110-0000-X
C
Test mode, user don
t use.
NORMAL
1 0 0
1110-0011-X
C
Normal mode
Yes
Note:
X : Don
,
t care
A5~A0 : RAM addresses
D3~D0 : RAM data
D/C : Data/command mode
Def. : Power on reset default
All the bold forms, namely 1 1 0, 1 0 1, and 1 0 0, are mode commands. Of these, 1 0 0 indicates the command
mode ID. If successive commands have been issued, the command mode ID except for the first command will
be omitted. The source of the tone frequency and of the time base/WDT clock frequency can be derived from
an on-chip 256kHz RC oscillator, a 32.768kHz crystal oscillator, or an external 256kHz clock. Calculation of the
frequency is based on the system frequency sources as stated above. It is recommended that the host control-
ler should initialize the HT1621 after power on reset, for power on reset may fail, which in turn leads to the mal-
functioning of the HT1621.
Package Information
48-pin SSOP (300mil) Outline Dimensions
Symbol
Dimensions in mil
Min.
Nom.
Max.
A
395
420
B
291
299
C
8
12
C
613
637
D
85
99
E
25
F
4
10
G
25
35
H
4
12
a
0
8
HT1621
Rev. 1.30
14
August 6, 2003
4 8
1
2 5
2 4
A
B
C
D
F
C '
G
H
a
E
48-pin DIP (600mil) Outline Dimensions
Symbol
Dimensions in mil
Min.
Nom.
Max.
A
2435
2445
B
535
555
C
145
155
D
125
145
E
16
20
F
50
70
G
100
H
595
615
I
635
670
a
0
15
HT1621
Rev. 1.30
15
August 6, 2003
4 8
1
2 5
2 4
a
A
B
C
D
E
F
G
H
I
48-pin LQFP (7
7) Outline Dimensions
Symbol
Dimensions in mm
Min.
Nom.
Max.
A
8.90
9.10
B
6.90
7.10
C
8.90
9.10
D
6.90
7.10
E
0.50
F
0.20
G
1.35
1.45
H
1.60
I
0.10
J
0.45
0.75
K
0.10
0.20
a
0
7
HT1621
Rev. 1.30
16
August 6, 2003
3 6
2 5
3 7
2 4
1 3
1 2
1
4 8
A
B
C
D
E
F
G
H
I
J
K
a
28-pin SKDIP (300mil) Outline Dimensions
Symbol
Dimensions in mil
Min.
Nom.
Max.
A
1375
1395
B
278
298
C
125
135
D
125
145
E
16
20
F
50
70
G
100
H
295
315
I
330
375
a
0
15
HT1621
Rev. 1.30
17
August 6, 2003
2 8
1
1 5
1 4
a
A
B
C
D
E
F
G
H
I
Product Tape and Reel Specifications
Reel Dimensions
SSOP 48W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330
1.0
B
Reel Inner Diameter
100
0.1
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0
0.5
T1
Space Between Flange
32.2+0.3
-0.2
T2
Reel Thickness
38.2
0.2
HT1621
Rev. 1.30
18
August 6, 2003
A
C
B
T 1
T 2
D
Carrier Tape Dimensions
SSOP 48W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
32.0
0.3
P
Cavity Pitch
16.0
0.1
E
Perforation Position
1.75
0.1
F
Cavity to Perforation (Width Direction)
14.2
0.1
D
Perforation Diameter
2.0 Min.
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0
0.1
P1
Cavity to Perforation (Length Direction)
2.0
0.1
A0
Cavity Length
12.0
0.1
B0
Cavity Width
16.20
0.1
K1
Cavity Depth
2.4
0.1
K2
Cavity Depth
3.2
0.1
t
Carrier Tape Thickness
0.35
0.05
C
Cover Tape Width
25.5
HT1621
Rev. 1.30
19
August 6, 2003
P
D 1
P 1
P 0
D
E
F
t
K 2
B 0
A 0
W
K 1
C
HT1621
Rev. 1.30
20
August 6, 2003
Copyright
2003 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek
s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Sales Office)
11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Shanghai) Inc.
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor (Hong Kong) Ltd.
Block A, 3/F, Tin On Industrial Building, 777-779 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Holmate Semiconductor, Inc.
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
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