Document Outline
- Features
- General Description
- Block Diagram
- Pin Assignment
- Pin Description
- Absolute Maximum Rating
- D.C. Characteristics
- A.C. Characteristics
- Functional Description
- Product Identification Code
Pin Assignment
Pin Description
Pin Name
I/O/P
Description
VPP
P
Program voltage supply
A0~A18
I
Address inputs
DQ0~DQ7
I/O
Data inputs/outputs
VSS
Negative power supply, ground
CE
I
Chip enable
OE
I
Output enable
VCC
Positive power supply
Absolute Maximum Rating
Operation Temperature Commercial ..........................................................................................................0
C to +70C
Storage Temperature.............................................................................................................................
-65C to 125 C
Applied VCC Voltage with Respect to VSS................................................................................................
-0.6V to 7.0V
Applied Voltage on Input Pin with Respect to VSS.....................................................................................
-0.6V to 7.0V
Applied Voltage on Output Pin with Respect to VSS .........................................................................
-0.6V to V
CC
+0.5V
Applied Voltage on A9 Pin with Respect to VSS ......................................................................................
-0.6V to 13.5V
Applied VPP Voltage with Respect to VSS...............................................................................................
-0.6V to 13.5V
Applied READ Voltage (Functionality is guaranteed between these limits) ..............................................+4.5V to +5.5V
Note: These are stress ratings only. Stresses exceeding the range specified under
Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
HT27C040
Rev. 1.00
2
April 30, 2001
V C C
A 1 8
A 1 7
A 1 4
A 1 3
A 8
A 9
A 1 1
O E
A 1 0
C E
D Q 7
D Q 6
D Q 5
D Q 4
D Q 3
V P P
A 1 6
A 1 5
A 1 2
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0
D Q 0
D Q 1
D Q 2
V S S
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
H T 2 7 C 0 4 0
3 2 D I P - A / S O P - A
5
6
7
8
9
1 0
1 1
1 2
1 3
3
1
3
2
1
2
3
4
2 9
2 7
2 6
2 5
2 4
2 3
2 2
2 1
3
0
2 8
1
7
1
4
1
5
1
6
1
8
1
9
2
0
H T 2 7 C 0 4 0
3 2 P L C C - A
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0
D Q 0
A 1 4
A 8
A 9
A 1 1
A 1 0
D Q 7
A 1 3
D
Q
3
D
Q
1
D
Q
2
V
S
S
D
Q
4
D
Q
5
D
Q
6
A
1
8
V
C
C
V
P
P
A
1
6
A
1
5
A
1
2
A
1
7
C E
O E
D.C. Characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
CC
Conditions
Read operation
V
OH
Output High Level
5V
I
OH
=
-0.4mA
2.4
V
V
OL
Output Low Level
5V
I
OL
=2.1mA
0.45
V
V
IH
Input High Level
5V
2
V
CC
+0.5
V
V
IL
Input Low Level
5V
-0.3
0.8
V
I
LI
Input Leakage Current
5V
V
IN
=0 to 5.5V
-5
5
mA
I
LO
Output Leakage Current
5V
V
OUT
=0 to 5.5V
-10
10
mA
I
CC
VCC Active Current
5V
CE=V
IL
, f=5MHz
I
OUT
=0mA
30
mA
I
SB1
Standby Current (CMOS)
5V
CE=V
CC
0.3V
1
10
mA
I
SB2
Standby Current (TTL)
5V
CE=V
IH
1
mA
I
PP
VPP Read/Standby Current
5V
CE=OE=V
IL
V
PP
=V
CC
100
mA
Programming operation
V
OH
Output High Level
6V
I
OH
=
-0.4mA
2.4
V
V
OL
Output Low Level
6V
I
OL
=2.1mA
0.45
V
V
IH
Input High Level
6V
0.7V
CC
V
CC
+0.5
V
V
IL
Input Low Level
6V
-0.5
0.8
V
I
LI
Input Load Current
6V
V
IN
=V
IL
, V
IH
5.0
mA
V
H
A9 Product ID Voltage
6V
11.5
12.5
V
I
CC
VCC Supply Current
6V
40
mA
I
PP
VPP Supply Current
6V
CE=V
IL
10
mA
Capacitance
C
IN
Input Capacitance
5V
V
IN
=0V
8
12
pF
C
OUT
Output Capacitance
5V
V
OUT
=0V
8
12
pF
C
VPP
VPP Capacitance
5V
V
PP
=0V
18
25
pF
A.C. Characteristics
Ta=+25
C5C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
CC
Conditions
Read operation
t
ACC
Address to Output Delay
5V
CE=OE=V
IL
70
ns
t
CE
Chip Enable to Output Delay
5V
OE=V
IL
70
ns
t
OE
Output Enable to Output Delay
5V
CE=V
IL
30
ns
t
DF
CE or OE High to Output Float, Whichever
Occurred First
5V
25
ns
t
OH
Output Hold from Address, CE or OE,
Whichever Occurred First
5V
0
ns
HT27C040
Rev. 1.00
3
April 30, 2001
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
CC
Conditions
Programming operation
t
AS
Address Setup Time
6V
2
ms
t
OES
OE Setup Time
6V
2
ms
t
DS
Data Setup Time
6V
2
ms
t
AH
Address Hold Time
6V
0
ms
t
DH
Data Hold Time
6V
2
ms
t
DFP
Output Enable to Output Float Delay
6V
0
130
ns
t
VPS
VPP Setup Time
6V
2
ms
t
PW
CE Program Pulse Width
6V
50
75
105
ms
t
VCS
VCC Setup Time
6V
2
ms
t
CES
CE Setup Time
6V
2
ms
t
OE
Data Valid from OE
6V
150
ns
t
PRT
VPP Pulse Rise Time During Programming
6V
2
ms
Test waveforms and measurements
Output test load
HT27C040
Rev. 1.00
4
April 30, 2001
2 . 4 V
0 . 4 5 V
A C
M e a s u r e m e n t
L e v e l
A C D r i v i n g
L e v e l s
2 . 0 V
0 . 8 V
t
R
, t
F
< 20ns (10% to 90%)
1 . 3 V
( 1 N 9 1 4 )
O u t p u t P i n
C
L
3 . 3 k W
Note: C
L
=100pF including jig capacitance
Functional Description
Programming of the HT27C040
When the HT27C040 is delivered, the chip has all
4096K bits in the
ONE, or HIGH state. ZEROs are
loaded into the HT27C040 through programming.
The programming mode is entered when 12.5
0.2V is ap-
plied to the VPP pin, OE is at V
IH
, and CE is V
IL
. For pro-
gramming, the data to be programmed is applied with 8
bits in parallel to the data pins.
The programming flowchart in Figure 3 shows the fast
interactive programming algorithm. The interactive al-
gorithm reduces programming time by using 50
ms to
105
ms programming pulses and giving each address
only as many pulses as is necessary in order to reliably
program the data. After each pulse is applied to a given
address, the data in that address is verified. If the data
is not verified, additional pulses are given until it is veri-
fied or until the maximum number of pulses is reached
while sequencing through each address of the
HT27C040. This process is repeated while sequencing
through each address of the HT27C040. This part of
the programming algorithm is done at V
CC
=6.0V to as-
sure that each EPROM bit is programmed to a suffi-
ciently high threshold voltage. This ensures that all bits
have sufficient margin. After the final address is com-
pleted, the entire EPROM memory is read at
V
CC
=V
PP
=5.25
0.25V to verify the entire memory.
Program inhibit mode
Programming of multiple HT27C040 in parallel with dif-
ferent data is also easily accomplished by using the Pro-
gram Inhibit Mode. Except for CE, all like inputs of the
parallel HT27C040 may be common. A TTL low-level
program pulse applied to an HT27C040 CE input with
VPP=12.5
2V, and OE HIGH will program that
HT27C040. A high-level CE input inhibits the
HT27C040 from being programmed.
HT27C040
Rev. 1.00
5
April 30, 2001
Program verify mode
Verification should be performed on the programmed
bits to determine whether they were correctly pro-
grammed. The verification should be performed with OE
at V
IL
, and CE at V
IH
, and VPP at its programming volt-
age.
Auto product identification
The Auto Product Identification mode allows the reading
out of a binary code from an EPROM that will identify its
manufacturer and the type. This mode is intended for
programming to automatically match the device to be
programmed with its corresponding programming algo-
rithm. This mode is functional in the 25
C5C ambient
temperature range that is required when programming
the HT27C040.
To activate this mode, the programming equipment
must force 12.0
0.5V on the address line A9 of the
HT27C040. Two identifier bytes may then be se-
quenced from the device outputs by toggling address
line A0 from V
IL
to V
IH
, when A1=V
IH
. All other address
lines must be held at V
IH
during Auto Product Identifica-
tion mode.
Byte 0 (A0=V
IL
) represents the manufacturer code, and
byte 1 (A0=V
IH
), the device code. For HT27C040, these
two identifier bytes are given in the Operation mode
truth table. When A1=V
IL,
the HT27C040 will read out
the binary code of 7F, continuation code, to signify the
unavailability of manufacturer ID codes.
Read mode
The has two control functions, both of which must be
logically satisfied in order to obtain data at outputs. Chip
Enable (CE) is the power control and should be used for
device selection. Output Enable (OE) is the output con-
trol and should be used to gate data to the output pins,
independent of device selection. Assuming that ad-
dresses are stable, address access time (t
ACC
) is equal
to the delay from CE to output (t
CE
). Data is available at
the outputs (t
OE
) after the falling edge of OE, assuming
the CE has been LOW and addresses have been stable
for at least t
ACC
-t
OE
.
Standby mode
The HT27C040 has CMOS standby mode which re-
duces the maximum VCC current to 10
mA. It is placed in
CMOS standby when CE is at V
C C
0.3V. The
HT27C040 also has a TTL-standby mode which re-
duces the maximum VCC current to 1.0mA. It is placed
in TTL-standby when CE is at V
IH
. When in standby
mode, the outputs are in a high-impedance state, inde-
pendent of the OE input.
Two-line output control function
To accommodate multiple memory connections, a
two-line control function is provided to allow for:
Low memory power dissipation
Assurance that output bus contention will not occur
It is recommended that CE be decoded and used as the
primary device-selection function, while OE be made a
common connection to the READ line from the system
control bus. This assures that all deselected memory
devices are in their low-power standby mode and that
the output pins are only active when data is desired from
a particular memory device.
System considerations
During the switch between active and standby condi-
tions, transient current peaks are produced on the rising
and falling edges of Chip Enable. The magnitude of
these transient current peaks is dependent on the out-
put capacitance loading of the device. At a minimum, a
0.1
mF ceramic capacitor (high frequency, low inherent
inductance) should be used on each device between
VCC and VPP to minimize transient effects. In addition,
to overcome the voltage drop caused by the inductive
effects of the printed circuit board traces on EPROM ar-
rays, a 4.7
mF bulk electrolytic capacitor should be used
between VCC and VPP for each eight devices. The lo-
cation of the capacitor should be close to where the
power supply is connected to the array.
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