HT27LC010
CMOS 128K8-Bit OTP EPROM
Block Diagram
Rev. 1.30
1
December 8, 2003
Features
Operating voltage: +3.3V
Programming voltage
-
V
PP
=12.5V
0.2V
-
V
CC
=6.0V
0.2V
High-reliability CMOS technology
Latch-up immunity to 100mA from -1.0V to
V
CC
+1.0V
CMOS and TTL compatible I/O
Low power consumption
-
Active: 15mA max.
-
Standby: 1
mA typ.
128K
8-bit organization
Fast read access time: 90ns
Fast programming algorithm
Programming time 75
ms typ.
Two line controls (OE and CE)
Standard product identification code
Commercial temperature ranges (0
C to +70C)
32-pin DIP/SOP/TSOP/PLCC Package
General Description
The HT27LC010 chip family is a low-power, 1024K
(1,048,576) bit, +3.3V electrically one-time programma-
ble (OTP) read-only memories (EPROM). Organized
into 128K words with 8 bits per word, it features a fast
single address location programming, typically at 75
ms
per byte. Any byte can be accessed in less than 90ns
with respect to Spec. This eliminates the need for WAIT
states in high-performance microprocessor systems.
The HT27LC010 has separate Output Enable (OE) and
Chip Enable (CE) controls which eliminate bus conten-
tion issues.
C E & O E &
P G M & T E S T
C o n t r o l L o g i c
X - D e c o d e r
Y - D e c o d e r
C e l l A r r a y
S A C K T
&
O u t p u t B u f f e r
C o l u m n
A d d r e s s
R o w
A d d r e s s
Y - G a t i n g
V C C
D Q 0 ~ D Q 7
G N D
C E
O E
P G M
V P P
Pin Assignment
Pin Description
Pin Name
I/O/C/P
Description
VPP
P
Program voltage supply
A0~A16
I
Address inputs
DQ0~DQ7
I/O
Data inputs/outputs
CE
C
Chip enable
OE
C
Output enable
PGM
C
Program strobe
NC
No connection
VCC
Positive power supply
Absolute Maximum Rating
Operation Temperature Commercial ..........................................................................................................0
C to +70C
Storage Temperature.............................................................................................................................
-65C to 125 C
Applied VCC Voltage with Respect to GND...............................................................................................
-0.6V to 7.0V
Applied Voltage on Input Pin with Respect to GND....................................................................................
-0.6V to 7.0V
Applied Voltage on Output Pin with Respect to GND.........................................................................
-0.6V to V
CC
+0.5V
Applied Voltage on A9 Pin with Respect to GND .....................................................................................
-0.6V to 13.5V
Applied VPP Voltage with Respect to GND ..............................................................................................
-0.6V to 13.5V
Applied READ Voltage (Functionality is guaranteed between these limits) ..............................................+3.0V to +3.6V
Note: These are stress ratings only. Stresses exceeding the range specified under
Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
HT27LC010
Rev. 1.30
2
December 8, 2003
H T 2 7 L C 0 1 0
3 2 D I P - A / S O P - A
5
6
7
8
9
1 0
1 1
1 2
1 3
3
1
3
2
1
2
3
4
2 9
2 7
2 6
2 5
2 4
2 3
2 2
2 1
3
0
2 8
1
7
1
4
1
5
1
6
1
8
1
9
2
0
H T 2 7 L C 0 1 0
3 2 P L C C - A
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0
D Q 0
A 1 4
A 8
A 9
A 1 1
A 1 0
D Q 7
A 1 3
D
Q
3
D
Q
1
D
Q
2
G
N
D
D
Q
4
D
Q
5
D
Q
6
P
G
M
V
C
C
V
P
P
A
1
6
A
1
5
A
1
2
N
C
C E
O E
V C C
P G M
N C
A 1 4
A 1 3
A 8
A 9
A 1 1
O E
A 1 0
C E
D Q 7
D Q 6
D Q 5
D Q 4
D Q 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
V P P
A 1 6
A 1 5
A 1 2
A 7
A 6
A 5
A 4
A 3
A 2
A 1
A 0
D Q 0
D Q 1
D Q 2
G N D
1
2
3
4
5
6
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
A 1 1
A 9
A 8
A 1 3
A 1 4
N C
P G M
V C C
V P P
A 1 6
A 1 5
A 1 2
A 7
A 6
A 5
A 4
O E
A 1 0
C E
D Q 7
D Q 6
D Q 5
D Q 4
D Q 3
G N D
D Q 2
D Q 1
D Q 0
A 0
A 1
A 2
A 3
H T 2 7 L C 0 1 0
3 2 T S O P - A
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
HT27LC010
Rev. 1.30
5
December 8, 2003
Functional Description
Operation Mode
All the operation modes are shown in the table following.
Mode
CE
OE
PGM
A0
A1
A9
VPP
Output
Read
V
IL
V
IL
X (2)
X
X
X
V
CC
Dout
Output Disable
V
IL
V
IH
X
X
X
X
V
CC
High Z
Standby (TTL)
V
IH
X
X
X
X
X
V
CC
High Z
Standby (CMOS)
V
CC
0.3V
X
X
X
X
X
V
CC
High Z
Program
V
IL
V
IH
V
IL
X
X
X
V
PP
D
IN
Program Verify
V
IL
V
IL
V
IH
X
X
X
V
PP
D
OUT
Product Inhibit
V
IH
X
X
X
X
X
V
PP
High Z
Manufacturer Code (3)
V
IL
V
IL
X
V
IL
V
IH
V
H
(1)
V
CC
1C
Device Code (3)
V
IL
V
IL
X
V
IH
V
IH
V
H
(1)
V
CC
01
Notes: (1)
V
H
12.0V 0.5V
(2)
X Either V
IH
or V
IL
(3) For Manufacturer Code and Device Code, A1=V
IH
, When A1=V
IL
, both codes will read 7F
Programming of the HT27LC010
When the HT27LC010 is delivered, the chip has all
1024K bits in the
ONE, or HIGH state. ZEROs are
loaded into the HT27LC010 through programming.
The programming mode is entered when 12.5
0.2V is
applied to the VPP pin, OE is at V
IH
, and CE and PGM are
V
IL
. For programming, the data to be programmed is ap-
plied with 8 bits in parallel to the data pins.
The programming flowchart in Figure 3 shows the fast
interactive programming algorithm. The interactive al-
gorithm reduces programming time by using 30
ms to
105
ms programming pulses and giving each address
only as many pulses as is necessary in order to reliably
program the data. After each pulse is applied to a given
address, the data in that address is verified. If the data is
not verified, additional pulses are given until it is verified
or until the maximum number of pulses is reached while
sequencing through each address of the HT27LC010.
This process is repeated while sequencing through
each address of the HT27LC010. This part of the pro-
gramming algorithm is done at V
CC
=6.0V to assure that
each EPROM bit is programmed to a sufficiently high
threshold voltage. This ensures that all bits have suffi-
cient margin. After the final address is completed, the
entire EPROM memory is read at V
CC
=V
PP
=3.3
0.3V to
verify the entire memory.
Program Inhibit Mode
Programming of multiple HT27LC010 in parallel with dif-
ferent data is also easily accomplished by using the Pro-
gram Inhibit Mode. Except for CE, all like inputs of the
parallel HT27LC010 may be common. A TTL low-level
program pulse applied to an HT27LC010 CE input with
Vpp=12.5
0.2V, PGM LOW, and OE HIGH will program
that HT27LC010. A high-level CE input inhibits the
HT27LC010 from being programmed.
Program Verify Mode
Verification should be performed on the programmed
bits to determine whether they were correctly pro-
grammed. The verification should be performed with OE
and CE at V
IL
, PGM at V
IH
, and VPP at its programming
voltage.
Auto Product Identification
The Auto Product Identification mode allows the reading
out of a binary code from an EPROM that will identify its
manufacturer and the type. This mode is intended for
programming to automatically match the device to be
programmed with its corresponding programming algo-
rithm. This mode is functional in the 25
C5C ambient
temperature range that is required when programming
the HT27LC010.
To activate this mode, the programming equipment must
force 12.0
0.5V on the address line A9 of the
HT27LC010. Two identifier bytes may then be se-
quenced from the device outputs by toggling address
line A0 from V
IL
to V
IH
, when A1=V
IH
. All other address
lines must be held at V
IH
during Auto Product Identifica-
tion mode.
Byte 0 (A0=V
IL
) represents the manufacturer code, and
byte 1 (A0=V
IH
), the device code. For HT27LC010,
these two identifier bytes are given in the Mode Select
Table. All identifiers for the manufacturer and device
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