HT36A4
8-Bit Music Synthesizer MCU
Block Diagram
Pin Assignment
Rev. 1.00
1
July 2, 2003
Features
Operating voltage: 2.4V~5.0V
Operating frequency: 3.58MHz~12MHz (typ. 8MHz)
8 bidirectional I/O lines
Two 8-bit programmable timer with 8 stage prescaler
Watchdog Timer
Built-in 8-bit MCU with 208
8 bits RAM
Built-in 32K
16-bit ROM for program/data shared
Mono output
High D/A converter resolution: 16 bits
Polyphonic up to 8 notes
Independent volume mix can be assigned to each
sound component
Sampling rate of 25kHz as 6.4MHz for system
frequency
Eight-level subroutine nesting
HALT function and wake-up feature to reduce power
consumption
Bit manipulation instructions
16-bit table read instructions
63 powerful instructions
All instructions in 1 or 2 machine cycles
16-pin DIP, 20-pin SOP package
General Description
The HT36A4 is an 8-bit high performance RISC-like
microcontroller specifically designed for music applica-
tions. It provides an 8-bit MCU and a 8 channel
wavetable synthesizer. The program ROM is composed
of both program control codes and wavetable voice
codes, and can be easily programmed.
The HT36A4 has a built-in 8-bit microprocessor which
programs the synthesizer to generate the melody by
setting the special register from 20H~2AH. A HALT fea-
ture is provided to reduce power consumption.
8 - B i t
M C U
3 2 K 1 6 - b i t
R O M
2 0 8 8
R A M
M u l t i p l i e r / P h a s e
G e n e r a l
P A 0 ~ P A 7
O S C 1
O S C 2
R E S
1 6 - B i t
D A C
V D D
V S S
V D D A
A U D
V S S A
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
1
2
3
4
5
6
7
8
H T 3 6 A 4
1 6 D I P - A
P A 4
P A 5
P A 6
P A 7
V S S
V D D
V D D A
T E S T
P A 3
P A 2
P A 1
P A 0
O S C 2
O S C 1
R E S
A U D
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1
2
3
4
5
6
7
8
9
1 0
P A 4
P A 5
P A 6
P A 7
V S S
V S S A
V D D
N C
V D D A
T E S T
P A 3
P A 2
P A 1
P A 0
N C
O S C 2
O S C 1
N C
R E S
A U D
H T 3 6 A 4
2 0 S O P - A
Pad Assignment
Chip size: 84.3
100.8 (mil)
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pad Coordinates
Unit:
mm
Pad No.
X
Y
Pad No.
X
Y
1
-903.425
1096.250
10
900.650
-994.626
2
-903.425
985.650
11
900.650
-316.774
3
-882.900
-650.050
12
901.625
1006.000
4
-882.900
-776.910
13
901.625
1116.600
5
-831.950
-886.910
14
697.050
1114.025
6
-831.950
-1025.350
15
586.450
1114.025
7
-177.390
-1045.600
16
-588.250
1114.025
8
-65.590
-1045.600
17
-698.850
1114.025
9
900.650
-1107.950
HT36A4
Rev. 1.00
2
July 2, 2003
P A 0
P A 1
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
A U D
O S C 2
O S C 1
R E S
V S S
V D D
V D D A
T E S T
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1
2
3
4
5
6
7
8
1 7
( 0 , 0 )
V S S A
Pad Description
Pad Name
I/O
Internal
Connection
Function
PA0~PA7
I/O
Pull-High
or None
Bidirectional 8-bit Input/Output port, wake-up by mask option
VSSA
Negative power supply of DAC, ground
VSS
Negative power supply, ground
VDD
Positive power supply
VDDA
DAC power supply
TEST
No connection (open)
AUD
O
Audio output for driving a external transistor or for driving HT82V733
RES
I
Reset input, active low
OSC1
OSC2
I
O
OSC1 and OSC2 are connected to an RC network or a crystal (by mask option)
for the internal system clock. In the case of RC operation, OSC2 is the output ter-
minal for 1/8 system clock. The system clock may come from the crystal, the two
pins cannot be floating.
Absolute Maximum Ratings
Supply Voltage ............................ V
SS
-0.3V to V
SS
+6V
Storage Temperature ..........................
-50C to 125C
Input Voltage ............................ V
SS
-0
.
3V to V
DD
+0.3V
Operating Temperature .........................
-25C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under
Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
V
DD
Operating Voltage
2.4
3
5
V
I
DD
Operating Current
5V
No load
f
OSC
=8MHz
8
16
mA
I
STB
Standby Current (WDT Disabled)
5V
No load
System HALT
1
mA
I
OL
I/O Ports Sink Current
5V
V
OL
=0.5V
9.7
16.2
mA
I
OH
I/O Ports Source Current
5V
V
OH
=4.5V
-5.2
-8.7
mA
R
PH
Pull-High Resistance of I/O Ports
5V
V
IL
=0V
11
22
44
k
W
V
IH1
Input High Voltage for I/O Ports
5V
3.5
5
V
V
IL1
Input Low Voltage for I/O Ports
5V
0
1.5
V
V
IH2
Input High Voltage (RES)
5V
4
V
V
IL2
Input Low Voltage (RES)
5V
2.5
V
HT36A4
Rev. 1.00
3
July 2, 2003
A.C. Characteristics
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
MCU interface
f
OSC
System Frequency
5V
8MHz crystal
8
MHz
f
SYS
System Clock
5V
4
8
MHz
t
WDT
Watchdog Time-Out Period (RC)
Without WDT prescaler
9
17
35
ms
t
RES
External Reset Low Pulse Width
1
ms
Characteristics Curves
V vs F Characteristics Curve
HT36A4
Rev. 1.00
4
July 2, 2003
H T 3 6 A 4 V v s . F C h a r t ( F o r 4 . 5 V )
2 . 4
2 . 6
2 . 8
3
3 . 2
3 . 4
3 . 6
3 . 8
4
4 . 2
4 . 4
4 . 6
4 . 8
5
V
D D
( V )
4
5
6
7
8
9
1 0
F
r
e
q
u
e
n
c
y
(
M
H
z
)
1 4 5 k W / 8 M H z
1 9 0 k W / 6 M H z
4
5
6
7
8
9
1 0
2 . 4
2 . 6
2 . 8
3
3 . 2
3 . 4
3 . 6
3 . 8
4
4 . 2
4 . 4
4 . 6
4 . 8
5
H T 3 6 A 4 V v s . F C h a r t ( F o r 3 . 0 V )
F
r
e
q
u
e
n
c
y
(
M
H
z
)
V
D D
( V )
1 5 5 k W / 8 M H z
2 0 0 k W / 6 M H z
R vs F Characteristics Curve
HT36A4
Rev. 1.00
5
July 2, 2003
1 2 0
1 5 0
1 8 0
2 0 0
2 2 0
2 4 0
2 7 0
3 0 0
H T 3 6 A 4 R v s . F C h a r t
F
r
e
q
u
e
n
c
y
(
M
H
z
)
1 4
1 2
1 0
8
6
4
2
R ( k W )
3 . 0 V
4 . 5 V
Function Description
Execution Flow
The system clock for the HT36A4 is derived from either
a crystal or an RC oscillator. The oscillator frequency di-
vided by 2 is the system clock for the MCU and it is inter-
nally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in one cycle. If an instruction
changes the program counter, two cycles are required
to complete the instruction.
Program Counter
- PC
The 13-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
ecuted and its contents specify a maximum of 8192 ad-
dresses for each bank.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points
to the memory word containing the next instruction
code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to retrieve the proper instruction. Other-
wise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Once a control transfer takes place, an additional
dummy cycle is required.
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
F e t c h I N S T ( P C )
E x e c u t e I N S T ( P C - 1 )
F e t c h I N S T ( P C + 1 )
E x e c u t e I N S T ( P C )
F e t c h I N S T ( P C + 2 )
E x e c u t e I N S T ( P C + 1 )
P C
P C + 1
P C + 2
S y s t e m C l o c k o f M C U
( S y s t e m C l o c k / 2 )
P C
Execution flow
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