HT36F2
Music Synthesizer 8-Bit MCU
Block Diagram
Rev. 1.00
1
August 15, 2005
Features
Operating voltage: 2.4V~5.0V
Operating frequency:
Xtal: 6MHz~8MHz
R
OSC
: typ. 6MHz
Built-in 32K
16-bit (0.5M-bit) ROM for program/data
shared
Built-in 8 bit MCU with 208
8 bits RAM
Two 8 bit programmable timer with 8 stage prescaler
16 bidirectional I/O lines
Four polyphonic synthesizer
Mono 16-bit DAC
Oscillation modes: XTAL/RCOSC
Low voltage reset
Eight-level subroutine nesting
Watchdog timer
Supports 8-bit table read instruction (TBLP)
HALT function and wake-up feature reduce power
consumption
Bit manipulation instructions
63 powerful instructions
All instructions in 1 or 2 machine cycles
16/28-pin SOP package
General Description
The HT36F2 is an 8-bit high performance RISC archi-
tecture microcontroller specifically designed for various
music applications. It provides an 8-bit MCU and a
4-channel Wavetable synthesizer. It has a built-in 8-bit
microprocessor which controls the synthesizer to gen-
erate the melody by setting the special register. A HALT
feature is provided to reduce power consumption.
8 - B i t
M C U
3 2 K 1 6 - b i t
R O M
2 0 8 8
R A M
M u l t i p l i e r / P h a s e
G e n e r a l
P A 0 ~ P A 7
P B 0 ~ P B 7
O S C 1
O S C 2
R E S
1 6 - B i t
D A C
V D D
V S S
V D D A
A U D
V S S A
Technical Document
Tools Information
FAQs
Application Note
Pin Assignment
Pad Assignment
Chip size: 2135
2385 (mm)
2
* The IC substrate should be connected to VSS in the PCB layout artwork.
HT36F2
Rev. 1.00
2
August 15, 2005
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
H T 3 6 F 2
2 8 S O P - A
P B 1
P B 0
A U D
T E S T
V D D A
V S S A
O S C 2
O S C 1
V S S
V D D
R E S
N C
N C
N C
P B 2
P B 3
P B 4
P B 5
P B 6
P B 7
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
1
2
3
4
5
6
7
8
A U D
V D D A
V S S A
O S C 2
O S C 1
V S S
V D D
R E S
P A 7
P A 6
P A 5
P A 4
P A 3
P A 2
P A 1
P A 0
H T 3 6 F 2
1 6 S O P - A
2 2
2 3
P
A
0
P
A
1
P
A
2
P A 3
P A 4
P A 5
P A 6
P A 7
P
B
0
P
B
1
P
B
2
P
B
3
P
B
4
P
B
5
P B 6
P B 7
O S C 1
O S C 2
R E S
( 0 , 0 )
1
2
3
4
5
6
7
8
9
2 5 2 4
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
2 1
1 2
1 1
1 0
A U D
T E S T
V D D A
V S S A
V S S
V D D
Pad Coordinates
Unit:
mm
Pad No.
X
Y
Pad No.
X
Y
1
-876.150
1043.000
14
916.350
514.500
2
-876.150
931.200
15
916.350
625.100
3
-876.150
817.560
16
916.350
725.100
4
-876.150
715.600
17
916.350
835.700
5
-916.350
-63.124
18
916.350
935.700
6
-916.350
-740.976
19
916.350
1046.300
7
-916.350
-842.650
20
704.250
1041.550
8
-916.350
-942.650
21
593.650
1041.550
9
-916.350
-1044.324
22
493.650
1041.550
10
710.500
-1041.350
23
383.050
1041.550
11
810.500
-1041.350
24
283.050
1041.550
12
921.100
-1041.350
25
172.450
1041.550
13
916.350
414.500
Pad Description
Pad No.
Pad Name
I/O
Internal
Connection
Function
8, 7
VDD, VSS
Digital power supply, ground
3,4
VDDA, VSSA
DAC power supply
10~17
PA0~PA7
I/O
Wake-up,
Pull-high or
None
Bidirectional 8-bit I/O port, wake-up by mask option
25~18
PB0~PB7
I/O
Pull-high or
None
Bidirectional 8-bit I/O port
9
RESET
I
Reset input, active low
6
OSC1
I
X
tal/Resistor XIN for Xtal or ROSCIN for resistor by mask option
5
OSC2
O
XOUT or T1
1
AUD
O
DAC output interface
Absolute Maximum Ratings
Supply Voltage ..........................V
SS
-0.3V to V
SS
+5.5V
Storage Temperature ...........................
-50C to 125C
Input Voltage .............................V
SS
-0
.
3V to V
DD
+0.3V
Operating Temperature ..........................
-25C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under
Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
HT36F2
Rev. 1.00
3
August 15, 2005
Electrical Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
V
DD
Operating Voltage
2.4
4.5
5
V
I
DD
Operating Current
3V
No load (OSC= 6MHz)
2
8
mA
4.5V
8
10
I
STB
Standby Current
3V
1
mA
4.5V
1
3
I
OH
Flag Source Current
3V
5
mA
4.5V
I
OL
Flag Sink Current
3V
5
mA
4.5V
V
IH
Input High Voltage for I/O Ports
0.8V
DD
V
DD
V
V
IL
Input Low Voltage for I/O Ports
0
0.2V
DD
V
HT36F2
Rev. 1.00
4
August 15, 2005
HT36F2
Rev. 1.00
5
August 15, 2005
Function Description
Execution Flow
The system clock for the HT36F2 is derived from either
a crystal or an RC oscillator. The oscillator frequency di-
vided by 2 is the system clock for the MCU and it is inter-
nally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in one cycle. If an instruction
changes the program counter, two cycles are required
to complete the instruction.
Program Counter
- PC
The 13-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
ecuted and its contents specify a maximum of 8192 ad-
dresses for each bank.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points
to the memory word containing the next instruction
code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to retrieve the proper instruction. Other-
wise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Once a control transfer takes place, an additional
dummy cycle is required.
Program ROM
HT36F2 provides 16 address lines WA15~WA0 to read
the Program ROM which is up to 0.5M bits, and is com-
monly used for the wavetable voice codes and the pro-
gram memory. It provides two address types, one type is
for program ROM, which is addressed by a bank pointer
PF1~PF0 and a 13-bit program counter PC12~PC0;
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
F e t c h I N S T ( P C )
E x e c u t e I N S T ( P C - 1 )
F e t c h I N S T ( P C + 1 )
E x e c u t e I N S T ( P C )
F e t c h I N S T ( P C + 2 )
E x e c u t e I N S T ( P C + 1 )
P C
P C + 1
P C + 2
S y s t e m C l o c k o f M C U
( S y s t e m C l o c k / 2 )
P C
Execution Flow
Mode
Program Counter
*14
*13
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Timer/Event Counter 0 Overflow PF1 PF0
0
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow PF1 PF0
0
0
0
0
0
0
0
0
0
1
1
0
0
Skip
Program Counter+2
Loading PCL
PF1 PF0 *12
*11
*10
*9
*8
@7 @6 @5 @4 @3 @2 @1 @0
Jump, Call Branch
PF1 PF0 #12 #11 #10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return From Subroutine
PF1 PF0 S12 S11 S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*12~*0: Bits of Program Counter
@7~@0: Bits of PCL
#12~#0: Bits of Instruction Code
S12~S0: Bits of Stack Register
@7~@0: Bits of PCL
PF1~PF0: Bits of Bank Register
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