HT46R232/HT46C232
A/D Type 8-Bit MCU
I
2
C is a trademark of Philips Semiconductors.
Rev. 1.40
1
November 23, 2005
General Description
The HT46R232/HT46C232 are 8-bit, high performance,
RISC architecture microcontroller devices specifically
designed for A/D applications that interface directly to
analog signals, such as those from sensors. The mask
version HT46C232 is fully pin and functionally compati-
ble with the OTP version HT46R232 device.
The advantages of low power consumption, I/O flexibil-
ity, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, Pulse
Width Modulation function, I
2
C interface, HALT and
wake-up functions, enhance the versatility of these de-
vices to suit a wide range of A/D application possibilities
such as sensor signal processing, motor driving, indus-
trial control, consumer products, subsystem controllers,
etc.
Features
Operating voltage:
f
SYS
=4MHz: 2.2V~5.5V
f
SYS
=8MHz: 3.3V~5.5V
40 bidirectional I/O lines (max.)
1 interrupt input shared with an I/O line
Two 16-bit programmable timer/event counter with
overflow interrupt
On-chip crystal and RC oscillator
Watchdog Timer
4096
16 program memory
192
8 data memory RAM
Supports PFD for sound generation
HALT function and wake-up feature reduce power
consumption
Up to 0.5
ms instruction cycle with 8MHz system clock
at V
DD
=5V
8-level subroutine nesting
8 channels 10-bit resolution A/D converter
4-channel 8-bit PWM output shared with
four I/O lines
Bit manipulation instruction
16-bit table read instruction
63 powerful instructions
All instructions in one or two machine cycles
Low voltage reset function
I
2
C Bus (slave mode)
28-pin SKDIP/SOP, 48-pin SSOP packages
Technical Document
Tools Information
FAQs
Application Note
-
HA0005E Controlling the I2C bus with the HT48 & HT46 MCU Series
-
HA0013E HT48 & HT46 LCM Interface Design
-
HA0017E Controlling the Read/Write Function of the HT24 Series EEPROM Using the HT49 Series MCUs
Block Diagram
Pin Assignment
HT46R232/HT46C232
Rev. 1.40
2
November 23, 2005
O S C 2
O S C 1
R E S
V D D
M U X
V S S
P r o g r a m
E P R O M
P r o g r a m
C o u n t e r
I n t e r r u p t
C i r c u i t
S T A C K
I N T C
D A T A
M e m o r y
I n s t r u c t i o n
R e g i s t e r
M
U
X
I n s t r u c t i o n
D e c o d e r
S T A T U S
A L U
S h i f t e r
T i m i n g
G e n e r a t o r
A C C
M P
L V R
H A L T
E N / D I S
M
U
X
M
U
X
W D T O S C
W D T
M
U
X
P F D 0
P F D 1
f
S Y S
/ 4
f
S Y S
P r e s c a l e r
T M R 0
f
S Y S
/ 4
P D C
P D
P D 0 / P W M 0 ~ P D 3 / P W M 3
P D 4 ~ P D 7
P B
P B C
P B 0 / A N 0 ~ P B 7 / A N 7
P W M
8 - C h a n n e l
A / D C o n v e r t e r
T M R 1
P F
P F C
P A C
P A
P A 0 ~ P A 2
P A 3 / P F D
P A 4
P A 5 / I N T
P A 6 / S D A
P A 7 / S C L
I
2
C B u s
S l a v e M o d e
P C
P C C
P C 0 ~ P C 7
B P
P A 5
P o r t F
P F 0 ~ P F 7
P o r t D
P o r t C
P o r t B
P o r t A
T M R 0 C
T M R 0
T M R 1 C
T M R 1
H T 4 6 R 2 3 2 / H T 4 6 C 2 3 2
4 8 S S O P - A
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
2 0
2 1
2 2
2 3
2 4
P B 5 / A N 5
P B 4 / A N 4
P A 3 / P F D
P A 2
P A 1
P A 0
P B 3 / A N 3
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
N C
P F 3
P F 2
P F 1
P D 7
P D 6
P D 5
P D 4
V S S
P F 0
T M R 0
P C 0
P C 1
P C 2
P B 6 / A N 6
P B 7 / A N 7
P A 4
P A 5 / I N T
P A 6 / S D A
P A 7 / S C L
P F 4
P F 5
P F 6
P F 7
O S C 2
O S C 1
V D D
R E S
T M R 1
P D 3 / P W M 3
P D 2 / P W M 2
P D 1 / P W M 1
P D 0 / P W M 0
P C 7
P C 6
P C 5
P C 4
P C 3
H T 4 6 R 2 3 2 / H T 4 6 C 2 3 2
2 8 S K D I P - A / S O P - A
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
P B 5 / A N 5
P B 4 / A N 4
P A 3 / P F D
P A 2
P A 1
P A 0
P B 3 / A N 3
P B 2 / A N 2
P B 1 / A N 1
P B 0 / A N 0
V S S
P C 0
P C 1
P C 2
P B 6 / A N 6
P B 7 / A N 7
P A 4
P A 5 / I N T
P A 6 / S D A
P A 7 / S C L
O S C 2
O S C 1
V D D
R E S
P D 1 / P W M 1 / T M R 1
P D 0 / P W M 0
P C 4
P C 3
Pin Description
Pin Name
I/O
Options
Description
PA0~PA2
PA3/PFD
PA4
PA5/INT
PA6/SDA
PA7/SCL
I/O
Pull-high
Wake-up
PA3 or PFD
I/O or Serial Bus
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
input by option (bit option). Software instructions determine the CMOS out-
put or Schmitt trigger input with or without pull-high resistor (determined by
pull-high options: bit option). The PFD and INT are pin-shared with PA3
and PA5, respectively. Once the I
2
C Bus function is used, the internal regis-
ters related to PA6 and PA7 cannot be used.
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
I/O
Pull-high
Bidirectional 8-bits input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (deter-
mined by pull-high option: bit option) or A/D input. Once a PB line is se-
lected as an A/D input (by using software control), the I/O function and
pull-high resistor are automatically disabled.
PC0~PC7
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (deter-
mine by pull-high option: byte option).
PD0/PWM0
PD1/PWM1
PD2/PWM2
PD3/PWM3
PD4~PD7
I/O
Pull-high
PWM
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor (de-
termined by pull-high option: byte option). The PWM0/PWM1/PWM2/
PWM3 output function are pin-shared with PD0/PD1/PD2/PD3 (depending
on the PWM options).
PF0~PF7
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (deter-
mine by pull-high option: byte option).
TMR0
I
Timer/Event Counter 0 Schmitt trigger input (without pull-high resistor)
TMR1
I
Timer/Event Counter 1 Schmitt trigger input (without pull-high resistor).
RES
I
Schmitt trigger reset input, active low
VSS
Negative power supply, ground
VDD
Positive power supply
OSC1
OSC2
I
O
Crystal or RC
OSC1 and OSC2 are connected to an RC network or a crystal (by options)
for the internal system clock. In the case of RC operation, OSC2 is the
output terminal for 1/4 system clock.
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V to V
SS
+6.0V
Storage Temperature ............................
-50C to 125C
Input Voltage..............................V
SS
-0.3V to V
DD
+0.3V
Operating Temperature...........................
-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under
Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
HT46R232/HT46C232
Rev. 1.40
3
November 23, 2005
D.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
V
DD
Operating Voltage
f
SYS
=4MHz
2.2
5.5
V
f
SYS
=8MHz
3.3
5.5
V
I
DD1
Operating Current (Crystal OSC)
3V
No load, f
SYS
=4MHz
ADC disable
0.6
1.5
mA
5V
2
4
mA
I
DD2
Operating Current (RC OSC)
3V
No load, f
SYS
=4MHz
ADC disable
0.8
1.5
mA
5V
2.5
4
mA
I
DD3
Operating Current
(Crystal OSC, RC OSC)
5V
No load, f
SYS
=8MHz
ADC disable
4
8
mA
I
STB1
Standby Current (WDT Enabled)
3V
No load, system HALT
5
mA
5V
10
mA
I
STB2
Standby Current (WDT Disabled)
3V
No load, system HALT
1
mA
5V
2
mA
V
IL1
Input Low Voltage for I/O Ports,
TMR0, TMR1 and INT
0
0.3V
DD
V
V
IH1
Input High Voltage for I/O Ports,
TMR0, TMR1 and INT
0.7V
DD
V
DD
V
V
IL2
Input Low Voltage (RES)
0
0.4V
DD
V
V
IH2
Input High Voltage (RES)
0.9V
DD
V
DD
V
V
LVR
Low Voltage Reset Voltage
2.7
3
3.3
V
I
OL
I/O Port Sink Current
3V
V
OL
=0.1V
DD
4
8
mA
5V
10
20
mA
I
OH
I/O Port Source Current
3V
V
OH
=0.9V
DD
-2
-4
mA
5V
-5
-10
mA
R
PH
Pull-high Resistance
3V
20
60
100
k
W
5V
10
30
50
k
W
V
AD
A/D Input Voltage
0
V
DD
V
E
AD
A/D Conversion Error
0.5
1
LSB
I
ADC
Additional Power Consumption
if A/D Converter is Used
3V
0.5
1
mA
5V
1.5
3
mA
HT46R232/HT46C232
Rev. 1.40
4
November 23, 2005
A.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
f
SYS
System Clock
2.2V~5.5V
400
4000
kHz
3.3V~5.5V
400
8000
kHz
f
TIMER
Timer I/P Frequency
(TMR0/TMR1)
2.2V~5.5V
0
4000
kHz
3.3V~5.5V
0
8000
kHz
t
WDTOSC
Watchdog Oscillator Period
3V
45
90
180
ms
5V
32
65
130
ms
t
RES
External Reset Low Pulse Width
1
ms
t
SST
System Start-up Timer Period
Wake-up from HALT
1024
*t
SYS
t
INT
Interrupt Pulse Width
1
ms
t
AD
A/D Clock Period
1
ms
t
ADC
A/D Conversion Time
76
t
AD
t
ADCS
A/D Sampling Time
32
t
AD
t
IIC
I
2
C Bus Clock Period
Connect to external
pull-high resistor 2k
W
64
*t
SYS
Note: *t
SYS
=1/f
SYS
HT46R232/HT46C232
Rev. 1.40
5
November 23, 2005
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