HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
Cost-Effective I/O Type 8-Bit MCU
Block Diagram
Rev. 1.10
1
June 9, 2004
General Description
The HT48R05A-1/HT48C05 and HT48R06A-1/
HT48C06 are 8-bit high performance, RISC architec-
ture microcontroller devices specifically designed for
cost-effective multiple I/O control product applications.
The mask version HT48C05 and HT48C06 are fully pin
and functionally compatible with the OTP version
HT48R05A-1 and HT48R06A-1 devices.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Features
Operating voltage:
f
SYS
=4MHz: 2.2V~5.5V
f
SYS
=8MHz: 3.3V~5.5V
13 bidirectional I/O lines
An interrupt input shared with an I/O line
8-bit programmable timer/event counter with over-
flow interrupt and 8-stage prescaler
On-chip crystal and RC oscillator
Watchdog Timer
Program memory ROM:
512
14 for HT48R05A-1/HT48C05
1024
14 for HT48R06A-1/HT48C06
Data memory RAM
32
8 for HT48R05A-1/HT48C05
64
8 for HT48R06A-1/HT48C06
Buzzer driving pair and PFD supported
HALT function and wake-up feature reduce power
consumption
Up to 0.5
ms instruction cycle with 8MHz system clock
at V
DD
=5V
Allinstructionsinoneortwomachinecycles
14-bit table read instruction
Two-level subroutine nesting
Bit manipulation instruction
Powerful instructions:
62 for HT48R05A-1/HT48C05
63 for HT48R06A-1/HT48C06
Low voltage reset function
16-pin SSOP package
18-pin DIP/SOP package
I N T / P C 0
O S C 2
O S C 1
R E S
V D D
M U X
P A C
P A
P O R T A
P A 0 ~ P A 7
f
S Y S
/ 4
W D T S
W D T
P C C
P C
P O R T C
P C 0 ~ P C 1
P B C
P B
P O R T B
P B 0 ~ P B 2
V S S
B Z / B Z
P C 0
P r o g r a m
R O M
P r o g r a m
C o u n t e r
I n t e r r u p t
C i r c u i t
S T A C K 0
S T A C K 1
I N T C
D A T A
M e m o r y
I n s t r u c t i o n
R e g i s t e r
M
U
X
I n s t r u c t i o n
D e c o d e r
S T A T U S
A L U
S h i f t e r
T i m i n g
G e n e r a t o r
A C C
R C O S C
W D T P r e s c a l e r
M
U
X
M P
T M R / P C 1
T M R
T M R C
P r e s c a l e r
f
S Y S
P C 1
M
U
X
Pin Assignment
Pad Assignment
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pad Description
Pad Name
I/O
Options
Description
PA0~PA7
I/O
Pull-high*
Wake-up
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
input by options. Software instructions determine the CMOS output or
Schmitt trigger input with a pull-high resistor (determined by pull-high op-
tions).
PB0/BZ
PB1/BZ
PB2
I/O
Pull-high*
I/O or BZ/BZ
Bidirectional 3-bit input/output port. Software instructions determine the
CMOS output or Schmitt trigger input with a pull-high resistor (determined by
pull-high options).
The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once the
PB0 and PB1 are selected as buzzer driving outputs, the output signals come
from an internal PFD generator (shared with a timer/event counter).
VSS
Negative power supply, ground
PC0/INT
PC1/TMR
I/O
Pull-high*
Bidirectional I/O lines. Software instructions determine the CMOS output or
Schmitt trigger input with a pull-high resistor (determined by pull-high op-
tions). The external interrupt and timer input are pin-shared with the PC0 and
PC1, respectively. The external interrupt input is activated on a high to low
transition.
HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
Rev. 1.10
2
June 9, 2004
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P C 1 / T M R
P A 3
P A 2
P A 1
P A 0
P B 2
P B 1 / B Z
P B 0 / B Z
V S S
P C 0 / I N T
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0
1
2
3
4
5
6
7
8
9
H T 4 8 R 0 5 A - 1 / H T 4 8 C 0 5
H T 4 8 R 0 6 A - 1 / H T 4 8 C 0 6
1 8 D I P - A / S O P - A
1 6
1 5
1 4
1 3
1 2
1 1
1 0
9
1
2
3
4
5
6
7
8
H T 4 8 R 0 5 A - 1 / H T 4 8 C 0 5
H T 4 8 R 0 6 A - 1 / H T 4 8 C 0 6
1 6 S S O P - A
P A 4
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P A 3
P A 2
P A 1
P A 0
P B 0 / B Z
V S S
P C 0 / I N T
P C 1 / T M R
( 0 , 0 )
1
2
3
4
5
6
7
8
9
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
P A 0
P B 2
P B 1 / B Z
P
B
0
/
B
Z
V
S
S
P
C
0
/
I
N
T
P
C
1
/
T
M
R
R
E
S
V
D
D
O
S
C
1
O S C 2
P A 7
P
A
6
P
A
5
P
A
4
P
A
3
P
A
2
P
A
1
Pad Name
I/O
Options
Description
RES
I
Schmitt trigger reset input. Active low
VDD
Positive power supply
OSC1
OSC2
I
O
Crystal
or RC
OSC1, OSC2 are connected to an RC network or Crystal (determined by op-
tions) for the internal system clock. In the case of RC operation, OSC2 is the
output terminal for 1/4 system clock.
* All pull-high resistors are controlled by an option bit.
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V to V
SS
+6.0V
Storage Temperature ............................
-50C to 125C
Input Voltage..............................V
SS
-0.3V to V
DD
+0.3V
Operating Temperature...........................
-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under
Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
D.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
V
DD
Operating Voltage
f
SYS
=4MHz
2.2
5.5
V
f
SYS
=8MHz
3.3
5.5
V
I
DD1
Operating Current (Crystal OSC)
3V
No load, f
SYS
=4MHz
0.6
1.5
mA
5V
2
4
mA
I
DD2
Operating Current (RC OSC)
3V
No load, f
SYS
=4MHz
0.8
1.5
mA
5V
2.5
4
mA
I
DD3
Operating Current (Crystal OSC)
5V
No load, f
SYS
=8MHz
3
5
mA
I
STB1
Standby Current (WDT Enabled)
3V
No load, system HALT
5
mA
5V
10
mA
I
STB2
Standby Current (WDT Disabled)
3V
No load, system HALT
1
mA
5V
2
mA
V
IL1
Input Low Voltage for I/O Ports,
TMR and INT
0
0.3V
DD
V
V
IH1
Input High Voltage for I/O Ports,
TMR and INT
0.7V
DD
V
DD
V
V
IL2
Input Low Voltage (RES)
0
0.4V
DD
V
V
IH2
Input High Voltage (RES)
0.9V
DD
V
DD
V
V
LVR
Low Voltage Reset
LVRenabled
2.7
3.0
3.3
V
I
OL
I/O Port Sink Current
3V
V
OL
=0.1V
DD
4
8
mA
5V
10
20
mA
I
OH
I/O Port Source Current
3V
V
OH
=0.9V
DD
-2
-4
mA
5V
-5
-10
mA
R
PH
Pull-high Resistance
3V
20
60
100
k
W
5V
10
30
50
k
W
HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
Rev. 1.10
3
June 9, 2004
A.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
f
SYS1
System Clock (Crystal OSC)
2.2V~5.5V
400
4000
kHz
3.3V~5.5V
400
8000
kHz
f
SYS2
System Clock (RC OSC)
2.2V~5.5V
400
4000
kHz
3.3V~5.5V
400
8000
kHz
f
TIMER
Timer I/P Frequency (TMR)
2.2V~5.5V
0
4000
kHz
3.3V~5.5V
0
8000
kHz
t
WDTOSC
Watchdog Oscillator Period
3V
45
90
180
ms
5V
32
65
130
ms
t
WDT1
Watchdog Time-out Period (RC)
3V
Without WDT prescaler
11
23
46
ms
5V
8
17
33
ms
t
WDT2
Watchdog Time-out Period
(System Clock)
Without WDT prescaler
1024
t
SYS
t
RES
External Reset Low Pulse Width
1
ms
t
SST
System Start-up Timer Period
Wake-up from HALT
1024
t
SYS
t
INT
Interrupt Pulse Width
1
ms
HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
Rev. 1.10
4
June 9, 2004
HT48R05A-1/HT48C05/HT48R06A-1/HT48C06
Rev. 1.10
5
June 9, 2004
Functional Description
Execution Flow
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
Program Counter
- PC
The program counter (PC) controls the sequence in
which the instructions stored in program ROM are exe-
cuted and its contents specify full range of program
memory.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
F e t c h I N S T ( P C )
E x e c u t e I N S T ( P C - 1 )
F e t c h I N S T ( P C + 1 )
E x e c u t e I N S T ( P C )
F e t c h I N S T ( P C + 2 )
E x e c u t e I N S T ( P C + 1 )
P C
P C + 1
P C + 2
S y s t e m C l o c k
O S C 2 ( R C o n l y )
P C
Execution Flow
Mode
Program Counter
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
1
0
0
0
Skip
PC+2
Loading PCL
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note: *9~*0: Program Counter bits
S9~S0: Stack register bits
#9~#0: Instruction code bits
@7~@0: PCL bits
For HT48R05A-1/HT48C05, the Program Counter is 9 bits wide, i.e. from *8~*0
For HT48R06A-1/HT48C06, the Program Counter is 10 bits wide, i.e. from *9~*0
PDF 
ZIP