HT48RA0-2/HT48CA0-2
Remote Type 8-Bit MCU
Block Diagram
Rev. 1.50
1
July 23, 2004
Features
Operating voltage: 2.0V~3.6V
Ten bidirectional I/O lines
4 Schmitt trigger input lines
One carrier output (1/2 or 1/3 duty)
On-chip crystal and RC oscillator
Watchdog Timer
1K
14 program memory
32
8 data RAM
HALT function and wake-up feature reduce power
consumption
62 powerful instructions
Up to 1
ms instruction cycle with 4MHz system clock
All instructions in 1 or 2 machine cycles
14-bit table read instructions
One-level subroutine nesting
Bit manipulation instructions
Low voltage reset function
20-pin SOP/SSOP package
General Description
The HT48RA0-2/HT48CA0-2 are 8-bit high perfor-
mance, RISC architecture microcontroller devices spe-
cifically designed for multiple I/O control product
applications. The mask version HT48CA0-2 is fully pin
and functionally compatible with the OTP version
HT48RA0-2 device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, watchdog timer,
HALT and wake-up functions, as well as low cost, en-
hance the versatility of this device to suit a wide range of
application possibilities such as industrial control, con-
sumer products, and particularly suitable for use in
products such as infrared remote controllers and vari-
ous subsystem controllers.
P r o g r a m
C o u n t e r
P r o g r a m
I n s t r u c t i o n
R e g i s t e r
I n s t r u c t i o n
D e c o d e r
T i m i n g
G e n e r a t o r
O S C 2
O S C 1
R E S
V D D
V S S
M P
M
U
X
M U X
D A T A
M e m o r y
A L U
S h i f t e r
S T A T U S
A C C
P A
P O R T A
P A 0 ~ P A 7
S Y S C L K / 4
W D T
F r e q u e n c y D i v i d e r
P B
P B 2 ~ P B 5
S T A C K
C a r r i e r C o n t r o l
L e v e l o r C a r r i e r
P C 0 / R E M
P C 0 C o n t r o l
P O R T B
P B 0 ~ P B 1
Pin Assignment
Pin Description
Pin Name
I/O
Code
Option
Description
PA0~PA7
I/O
Bidirectional 8-bit input/output port with pull-high resistors. Each bit can be de-
termined as NMOS output or Schmitt trigger input by software instructions.
PB0, PB1
I/O
Wake-up
or None
2-bit bidirectional input/output lines with pull-high resistors. Each bit can be de-
termined as NMOS output or Schmitt trigger input by software instructions.
Each bit can also be configured as wake-up input by code option.
PB2~PB5
I
Wake-up or
None
4-bit Schmitt trigger input lines with pull-high resistors. Each bit can be config-
ured as a wake-up input by code option.
PC0/REM
O
Level or
Carrier
Level or carrier output pin
PC0 can be set as CMOS output pin or carrier output pin by code option.
VDD
Positive power supply
VSS
Negative power supply, ground
OSC2
OSC1
O
I
Crystal
or RC
OSC1, OSC2 are connected to an RC network or a crystal (determined by
code option) for the internal system clock. In the case of RC operation, OSC2
is the output terminal for 1/4 system clock (NMOS open drain output).
RES
I
Schmitt trigger reset input. Active low.
Absolute Maximum Ratings
Supply Voltage ...........................V
SS
-0.3V to V
SS
+4.0V
Storage Temperature ............................
-50C to 125C
Input Voltage..............................V
SS
-0.3V to V
DD
+0.3V
Operating Temperature...........................
-40C to 85C
Note: These are stress ratings only. Stresses exceeding the range specified under
Absolute Maximum Ratings may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.
HT48RA0-2/HT48CA0-2
Rev. 1.50
2
July 23, 2004
P A 2
P A 3
P A 4
P A 5
P A 6
P A 7
P B 2
P B 3
P B 4
P B 5
P A 1
P A 0
P B 1
P B 0
P C 0 / R E M
V D D
O S C 2
O S C 1
V S S
R E S
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1
2
3
4
5
6
7
8
9
1 0
H T 4 8 R A 0 - 2 / H T 4 8 C A 0 - 2
2 0 S O P - A / S S O P - A
D.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
V
DD
Operating Voltage
2.0
3.6
V
I
DD
Operating Current
3V
No load, f
SYS
=4MHz
0.7
1.5
mA
I
STB
Standby Current
3V
No load, system HALT
1
mA
V
IL1
Input Low Voltage for I/O Ports
3V
0
0.3V
DD
V
V
IH1
Input High Voltage for I/O Ports
3V
0.7V
DD
V
DD
V
V
IL2
Input Low Voltage (RES)
3V
0
0.4V
DD
V
V
IH2
Input High Voltage (RES)
3V
0.9V
DD
V
DD
V
V
LVR
Low Voltage Reset Voltage
1.9
2.0
V
I
OL
I/O Ports Sink Current
3V
V
OL
=0.1V
DD
4
8
mA
I
OH
PC0/REM Output Source Current
3V
V
OH
=0.9V
DD
-2
-4
mA
R
PH
Pull-high Resistance
3V
20
60
100
k
W
A.C. Characteristics
Ta=25
C
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
V
DD
Conditions
f
SYS
System Clock
3V
400
4000
kHz
t
RES
External Reset Low Pulse Width
1
ms
t
SST
System Start-up Timer Period
Power-up, reset or wake-up
from HALT
1024
t
SYS
t
LVR
Low Voltage Width to Reset
1
ms
Note: t
SYS
=1/f
SYS
HT48RA0-2/HT48CA0-2
Rev. 1.50
3
July 23, 2004
Functional Description
Execution Flow
The HT48RA0-2/HT48CA0-2 system clock can be de-
rived from a crystal/ceramic resonator oscillator. It is in-
ternally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch takes one instruction cycle while de-
coding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruc-
tion to effectively execute within one cycle. If an instruc-
tion changes the program counter, two cycles are
required to complete the instruction.
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
F e t c h I N S T ( P C )
E x e c u t e I N S T ( P C - 1 )
F e t c h I N S T ( P C + 1 )
E x e c u t e I N S T ( P C )
F e t c h I N S T ( P C + 2 )
E x e c u t e I N S T ( P C + 1 )
P C
P C + 1
P C + 2
S y s t e m C l o c k
I n s t r u c t i o n C y c l e
P C
Execution Flow
HT48RA0-2/HT48CA0-2
Rev. 1.50
4
July 23, 2004
Program Counter
- PC
The 10-bit program counter (PC) controls the sequence
in which the instructions stored in program ROM are ex-
ecuted and its contents specify a maximum of 1024 ad-
dresses.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading PCL register, subroutine call, initial re-
set or return from subroutine, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
Program Memory
- ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data and table and is organized into 1024
14 bits, ad-
dressed by the program counter and table pointer.
Certain locations in the program memory are reserved
for special usage:
Location 000H
This area is reserved for the initialization program. Af-
ter chip reset, the program always begins execution at
location 000H.
Table location
Any location in the EPROM space can be used as
look-up tables. The instructions TABRDC [m] (the cur-
rent page, one page=256 words) and TABRDL [m]
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
Mode
Program Counter
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
0
0
0
0
0
0
0
0
0
0
Skip
PC+2
Loading PCL
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, call branch
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
*9~*0: Program counter bits
S9~S0: Stack register bits
#9~#0: Instruction code bits
@7~@0: PCL bits
0 0 0 H
D e v i c e i n i t i a l i z a t i o n p r o g r a m
P r o g r a m
1 4 b i t s
L o o k - u p t a b l e ( 2 5 6 w o r d s )
n 0 0 H
L o o k - u p t a b l e ( 2 5 6 w o r d s )
3 F F H
N o t e : n r a n g e s f r o m 0 t o 3
n F F H
Program Memory
Instruction(s)
Table Location
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*9~*0: Table location bits
@7~@0: Table pointer bits
P9~P8: Current program counter bits
HT48RA0-2/HT48CA0-2
Rev. 1.50
5
July 23, 2004
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, the remaining 2 bits are read as
0.
The Table Higher-order byte register (TBLH) is read
only. The table pointer (TBLP) is a read/write register
(07H), where P indicates the table location. Before ac-
cessing the table, the location must be placed in
TBLP. The TBLH is read only and cannot be restored.
All table related instructions need 2 cycles to complete
the operation. These areas may function as normal
program memory depending upon the requirements.
Stack Register
- STACK
This is a special part of the memory used to save the
contents of the program counter (PC) only. The stack is
organized into one level and is neither part of the data
nor part of the program space, and is neither readable
nor writeable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call the contents of the program counter are
pushed onto the stack. At the end of a subroutine sig-
naled by a return instruction (RET), the program counter
is restored to its previous value from the stack. After a
chip reset, the SP will point to the top of the stack.
If the stack is full and a
CALL is subsequently exe-
cuted, stack overflow occurs and the first entry will be
lost (only the most recent return address is stored).
Data Memory
- RAM
The data memory is designed with 42
8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(32
8). Most of them are read/write, but some are read
only.
The special function registers include the indirect ad-
dressing register (00H), the memory pointer register
(MP;01H), the accumulator (ACC;05H) the program
counter lower-order byte register (PCL;06H), the table
pointer (TBLP;07H), the table higher-order byte register
(TBLH;08H), the status register (STATUS;0AH) and the
I/O registers (PA;12H, PB;14H, PC;16H). The remaining
space before the 20H is reserved for future expanded
usage and reading these locations will return the result
00H. The general purpose data memory, addressed
from 20H to 3FH, is used for data and control informa-
tion under instruction command.
All data memory areas can handle arithmetic, logic, in-
crement, decrement and rotate operations directly. Ex-
cept for some dedicated bits, each bit in the data
memory can be set and reset by the SET [m].i and CLR
[m].i instructions, respectively. They are also indirectly
accessible through memory pointer register (MP;01H).
Indirect Addressing Register
Location 00H is an indirect addressing register that is
not physically implemented. Any read/write operation of
[00H] accesses data memory pointed to by MP (01H).
Reading location 00H itself indirectly will return the re-
sult 00H. Writing indirectly results in no operation.
The memory pointer register MP (01H) is a 6-bit register.
The bit 7~6 of MP is undefined and reading will return
the result
1. Any writing operation to MP will only trans-
fer the lower 6-bit data to MP.
Accumulator
The accumulator closely relates to ALU operations. It is
also mapped to location 05H of the data memory and is
capable of carrying out immediate data operations. Data
movement between two data memory locations has to
pass through the accumulator.
G e n e r a l P u r p o s e
D A T A M E M O R Y
( 3 2 B y t e s )
S p e c i a l P u r p o s e
D A T A M E M O R Y
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
3 F H
I n d i r e c t A d d r e s s i n g R e g i s t e r
M P
A C C
P C L
T B L P
T B L H
S T A T U S
P A
P B
P C
: U n u s e d
R e a d a s " 0 0 "
2 0 H
RAM Mapping
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