HT6116-70
CMOS 2K
8-Bit SRAM
Pin Assignment
Block Diagram
General Description
The HT6116-70 is a 16384-bit static random
access memory. It is organized with 2048 words
of 8 bits in length, and operates with a single 5V
power supply. The IC is built with a high per-
formance CMOS 0.8
m process in order to ob-
tain a low standby current and high reliability.
The IC contains six-transistor full CMOS mem-
ory cells and TTL compatible inputs and out-
puts, which are easily interface with common
system bus structures. The Data bus of the
HT6116-70 is designed as a tri-state type. The
IC is in the standby mode if the CS pin is set to
"high".
Features
Single 5V power supply
Low power consumption
Operating: 400mW (Typ.)
Standby: 5
W (Typ.)
70ns (Max.) high speed access time
Power down by pin CS
TTL compatible interface levels
Fully static operation
Memory expansion by pin OE
Common I/O using tri-state outputs
Pin-compatible with standard 2K
8 bits of
EPROM/MASK ROM
24-pin DIP/SDIP/SOP package
1
3rd July '97
Pin Description
Pin No.
Pin Name
I/O
Description
8~1,
23, 22, 19
A0~A7
A8, A9, A10
I
Address inputs
9~11
13~17
D0~D2
D3~D7
I/O
Data inputs and outputs
12
VSS
I
Negative power supply, usually connected to the ground
18
CS
I
Chip select signal pin
When this signal is high, the chip is in the standby mode. The
chip is in the active mode, if CS is low.
20
OE
I
Output enable signal pin
21
WE
I
Write enable signal pin
24
VDD
I
Positive power supply
Absolute Maximum Ratings*
Supply Voltage ............................0.3V to +7.0V
Storage Temperature...............50
C to +125
C
Input Voltage................. V
SS
0.3V to V
DD
+0.3V
Operating Temperature.............40
C to +85
C
*Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. These are stress ratings only. Functional operation of this device at
these or any other conditions above those indicated in the operational sections of this
specification is not implied and exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
D.C. Characteristics
(Ta=25C)
Symbol
Parameter
Test Conditions
Min.
Typ. Max.
Unit
V
DD
Conditions
V
DD
Operating Voltage
--
--
4.5
5.0
5.5
V
I
LI
Input Leakage Current
5V
V
IN
=0 to V
DD
--
0.1
10
A
I
LO
Output Leakage Current
5V
V
O
=0 to V
DD
--
0.1
10
A
I
DD
Operating Current
5V
V
IH
=2.2V, V
IL
=0.8V
In write mode, t
WC
=1
s.
--
45
90
mA
5V
V
IH
=2.2V, V
IL
=0.8V
In read mode, t
RC
=1
s.
--
80
90
mA
I
STB
Standby Current
5V
V
IH
=2.2V, V
IL
=0.8V
(TTL Input)
--
0.8
1.5
mA
5V
V
IH
=4.8V, V
IL
=0.2V
(CMOS Input)
--
0.1
3
A
HT6116-70
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3rd July '97
Symbol
Parameter
Test Conditions
Min.
Typ. Max.
Unit
V
DD
Conditions
V
IH
Input Voltage
5V
--
2.2
2
5.3
V
V
IL
5V
0.3
0.2
0.8
V
I
OH
Output Source Current
5V
V
OH
=4.5V
1.2
6.2
--
mA
I
OL
Output Sink Current
5V
V
OL
=0.5V
4.8
14.5
--
mA
A.C. Test Conditions
Item
Condition
Input pulse high level
V
IH
=3V
Input pulse low level
V
IL
=0V
Input and output reference level
1.5V
Output load
See Figures below
HT6116-70
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3rd July '97
A.C. Characteristics
Read cycle
(V
DD
=5V
10%, GND=0V, Ta=40
C to +85
C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
RC
Read Cycle Time
70
36
--
ns
t
AA
Address Access Time
--
35
70
ns
t
ACS
Chip Select Access Time
--
35
70
ns
t
OE
Output Enable to Output Valid
--
12
40
ns
t
OH
Output Hold from Address Change
10
12
--
ns
t
CLZ
Chip Enable to Output in Low-Z
10
--
--
ns
t
OLZ
Output Enable to Output in Low-Z
10
--
--
ns
t
OHZ
Output Disable to Output in HighZ
0
--
30
ns
t
CHZ
Chip Disable to Output in High-Z
0
--
30
ns
Note: 1. A read occurs during the overlap of a low CS and a high WE
2. t
CHZ
and t
OHZ
are specified by the time when data out is floating
Write cycle
(V
DD
=5V
10%, GND=0V, Ta=40
C to +85
C)
Symbol
Parameter
Min.
Typ.
Max.
Unit
t
WC
Write Cycle Time
70
36
--
ns
t
DW
Data Set up Time
20
18
--
ns
t
DH
Data Hold Time from Write Time
5
0
--
ns
t
AW
Address Valid to End of Write
50
15
--
ns
t
AS
Address Setup Time
20
14
ns
t
WP
Write Pulse Width
25
0
--
ns
t
WR
Write Recovery Time
5
--
--
ns
t
CW
Chip Selection to End of Write
35
--
--
ns
t
OW
Output Active from End of Write
5
--
--
ns
t
OHZ
Output Disable to Output in High-Z
0
--
40
ns
t
WHZ
Write to Output in High-Z
0
--
50
ns
Note: 1. A write cycle occurs during the overlap of a low CS and a low WE
2. OE may be both high and low in a write cycle
3. t
AS
is specified from CS or WE, whichever occurs last
4. t
WP
is an overlap time of a low CS and a low WE
5. t
WR
, t
DW
and t
DH
is specified from CS or WE, whichever occurs first
6. t
WHZ
is specified by the time when DATA OUT is floating, not defined by output level
7. When I/O pins are data output mode, don't force inverse signals to those pins
HT6116-70
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3rd July '97
Timing Diagrams
Read cycle
(1)
Functional Description
The HT6116-70 is a 2K
8 bit SRAM. When the
CS pin of the chip is set to "low", data can be
written in or read from eight data pins; other-
wise, the chip is in the standby mode. During a
write cycle, the data pins are defined as the
input state by setting the WE pin to low. Data
should be ready before the rising edge of the WE
pin according to the timing of the writing cycle.
While in the read cycle, the WE pin is set to high
and the OE pin is set to low to define the data
pins as the output state. All data pins are de-
fined as a three-state type, controlled by the OE
pin. In both cycles (namely, write and read cy-
cles), the locations are defined by the address
pins A0~A10. The following table illustrates the
relations of WE, OE, CS and their correspond-
ing mode.
CS
OE
WE
Mode
D0~D7
H
X
X
Standby
HighZ
L
L
H
Read
Dout
L
H
H
Read
HighZ
L
X
L
Write
Din
where
X stands for "don't care".
H stands for high level
L stands for low level.
HT6116-70
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3rd July '97
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