HT9302 Series

1-Memory/2-Memory Tone/Pulse Dialer

Selection Table

Function

Part No.

Lock Function

(Pin Selection)

Hold Line

Hand Free

LCD Interface

Package

HT9302x

(Normal version)

HT9302A

18 DIP

HT9302B

22 SKDIP

HT9302C

20 DIP

HT9302D

24 SKDIP

HT9302G

(Simple version)

HT9302G

16 DIP

Rev. 1.20

September 30, 2002

Features

Universal specification

Operating voltage: 2.0V~5.5V

Low standby current

Low memory retention current: 0.1

mA (typ.)

Tone/pulse switchable

Interface with LCD driver

32 digits for redialing

32 digits for SA memory dialing

One-key redialing

Pause and P

®T key for PBX

´4 keyboard matrix

3.58MHz crystal or ceramic resonator

Hand-free control

Hold-line control

Pause, P

®T can be saved for redialing

Lock function

Resistor options

M/B ratio

Flash function and flash time

Pause and P

®T duration

Pulse number

HT9302A: 18-pin DIP package
HT9302B: 22-pin SKDIP package
HT9302C: 20-pin DIP package
HT9302D: 24-pin SKDIP package
HT9302G: 16-pin DIP package

General Description

The HT9302 series tone/pulse dialers are CMOS LSIs
for telecommunication systems. They are designed to
meet various dialing specifications through resistor op-
tion matrix.

The HT9302 series provide the pin-selected lock func-

tion, Hold-line, Hand-free and LCD dialing number
display interface, all of which are suitable for feature
phone applications. HT9302G is simpler than HT9302X
version. It provides only a redialing memory for simple
low-cost system applications.

Patent Number: 64097, 86474, 64529, 113235 (R.O.C.)

5424740 (U.S.A.)

Block Diagram

Pin Assignment

HT9302x normal version

HT9302G simple version

HT9302 Series

Rev. 1.20

September 30, 2002

C 1

R 1

P O

H K S

H D I

K e y

C o l u m n

. S M

K e y

. u n c t i o n

E n c o d e r

C o n t r o l

W R M

C o u n t e r

A D D R L

K e y R o w

S R A M

D e b o u n c e

D i v i d e r

C l o c k

G e n e r a t o r

M / B

. l a s h

T i m e r

C h e c k

T o n e

E n c o d e r

C o n v e r t e r

T o n e

O u t

P u l s e

O u t

D T M .

H . I

M O D E

D O U T

C L O C K

X M U T E

C 4

R 4

X 1

X 2

K e y t o n e

G e n e r a t o r

C l o c k

C o n t r o l

L O C K

M o d e I n

H D / H .

H D O
H . O

R 4
R 3
R 2
R 1
M O D E
D T M .
P O
H K S

1 6
1 5
1 4
1 3
1 2
1 1
1 0

1
2
3
4
5
6
7
8

C 1
C 2
C 3

X 1
X 2

X M U T E

V S S

V D D

H T 9 3 0 2 G

1 6 D I P - A

H D I

C 1
C 2
C 3
C 4

L O C K

X 1
X 2

X M U T E

V S S

H . I

D O U T

C 1
C 2
C 3
C 4

L O C K

X 1
X 2

X M U T E

V S S

1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1
1 0

1
2
3
4
5
6
7
8
9

R 4
R 3
R 2
R 1
M O D E
D T M .
P O
H K S
V D D

H D I

C 1
C 2
C 3
C 4

L O C K

X 1
X 2

X M U T E

V S S

H . I

2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2

1
2
3
4
5
6
7
8
9
1 0
1 1

H D O
R 4
R 3
R 2
R 1
M O D E
D T M .
P O
H K S
V D D
H . O

C 1
C 2
C 3
C 4

L O C K

X 1
X 2

X M U T E

V S S

D O U T

2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3
1 2
1 1

1
2
3
4
5
6
7
8
9
1 0

R 4
R 3
R 2
R 1
M O D E
D T M .
P O
H K S
V D D
C L O C K

2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
1 4
1 3

1
2
3
4
5
6
7
8
9
1 0
1 1
1 2

H D O
R 4
R 3
R 2
R 1
M O D E
D T M .
P O
H K S
V D D
H . O
C L O C K

H T 9 3 0 2 D

2 4 S K D I P - A

H T 9 3 0 2 C

2 0 D I P - A

H T 9 3 0 2 B

2 2 S K D I P - A

H T 9 3 0 2 A

1 8 D I P - A

Keyboard Information

Pin Description

Pin Name

I/O

Internal

Connection

Description

C1~C4
R1~R4

I/O

CMOS IN/OUT

These pins form a 4

´4 keyboard matrix which can perform keyboard input detec-

tion and dialing specification setting functions. When on-hook (HKS=high) all the
pins are set high. While off-hook the column group (C1~C4) remains low and the
row group (R1~R4) is set high for key input detection.
An inexpensive single contact 4

´4 keyboard can be used as an input device.

Pressing a key connects a single column to a single row, and actuates the system
oscillator that results in a dialing signal output. If more than two keys are pressed at
the same time, no response occurs. The key-in debounce time is 20ms. Refer to
the keyboard information for keyboard arrangement and to the functional descrip-
tion for dialing specification selection.

OSCILLATOR

The system oscillator consists of an inverter, a bias resistor and the necessary
load capacitor on chip. Connecting a standard 3.579545MHz crystal or ceramic
resonator to the X1 and X2 terminals can implement the oscillator function. The
oscillator is turned off in the standby mode, and is actuated whenever a key-
board entry is detected.

XMUTE

NMOS OUT

XMUTE is an NMOS open drain structure pulled to VSS during dialing signal

transmission. Otherwise, it is an open circuit. The XMUTE is used to mute the
speech circuit when transmitting the dial signal.

HKS

CMOS IN

This pin is used to monitor the status of the hook-switch and its combination
with HFI/HDI can control the PO pin output to make or break the line.
HKS=VDD: On-hook state (PO=low). Except for HFI/HDI

(hand-free/hold-line control input), other functions are all disabled.

HKS=VSS: Off-hook state (PO=high). The chip is in the standby mode and

ready to receive the key input.

CMOS OUT

This pin is a CMOS output structure, which by receiving HKS and HFO/HDO
signals, control the dialer to connect or disconnect the telephone line.
PO outputs a low to break the line when HKS is high (on-hook) and HFO/HDO
is low. PO outputs a high to make the line when HKS is low (off-hook) or HFO is
high or HDO is high.
During the off-hook state, the pin also outputs the dialing pulse train in pulse
mode dialing. While in the tone mode, this pin is always high.

MODE

I/O

CMOS IN/OUT

This is a three-state input/output pin, used for dialing mode selection whether

Tone mode or Pulse mode; 10pps/20pps.
MODE=VDD: Pulse mode, 10pps
MODE=OPEN: Pulse mode, 20pps
MODE=VSS: Tone mode
During pulse mode dialing, switching this pin to the tone mode changes the
subsequent digit entry to tone mode. When the chips are in tone mode, switch-
ing to the pulse mode will also be recognized.

HT9302 Series

Rev. 1.20

September 30, 2002

H T 9 3 0 2 A / B / C / D

* / T

S A

R 4

R 3

R 2

R 1

C 4

C 1

C 2

C 3

H K S

H T 9 3 0 2 G

* / T

R 4

R 3

R 2

R 1

C 1

C 2

C 3

Pin Name

I/O

Internal

Connection

Description

DTMF

CMOS OUT

This pin is active only when the chip transmits tone dialing signals. Otherwise, it
always outputs a low. The pin outputs tone signals to drive the external trans-
mitter amplifier circuit. The load resistor should not be less than 5k

HDI

CMOS IN

Pull-high

This pin is a Schmitt trigger input structure. Active low. Applying a negative go-
ing pulse to this pin can toggle the HDO output once.
An external RC network is recommended for input debouncing. The Pull-high
resistance is 200k

W typ.

HDO

CMOS OUT

The HDO is a CMOS output structure. Its output is toggle- controlled by a nega-
tive transition on HDI. When HDO is toggled high, PO keeps high to hold the
line. The hold function can be released by setting HFO high or by an on-off hook
operation or by another HDI input. Refer to the functional description for the
hold-line function.

HFI

CMOS IN

Pull-low

This pin is a Schmitt trigger input structure. Active high. Applying a positive go-
ing pulse to HFI can toggle the HFO once and hence control the hand-free func-
tion. The Pull-low resistance of HFI is 200k

W typ.

An external RC network is recommended for input debouncing.

HFO

CMOS OUT

The HFO is a CMOS output structure. Its output is toggle- controlled by a posi-
tive transition on HFI pin. When HFO is high, the hand-free function is enabled
and PO outputs a high to connect the line.
The hand-free function can be released by setting HDO high or by an on-off-hook
operation or by another HFI input. Refer to the functional description for the
hand-free functional operation.

LOCK

I/O

CMOS IN/OUT

This is a three-state input/output pin, used for controlling long distance call
function with a lock-switch.
LOCK=OPEN: Normal dialing (no lock)
LOCK=VDD:

²0, 9² is inhibited for use as the first key input

LOCK=VSS:

²0² is inhibited for use as the first key input

DOUT

NMOS OUT

NMOS open drain output pin. It outputs the BCD code of the dialing digits to the

LCD driver chip (HT16XX series) or MCU for dialing number display. Refer to
the functional description for the detailed timing.

CLOCK

NMOS OUT

NMOS open drain output. When dialing, it outputs a series of pulse trains for
DOUT data synchronization. DOUT data is valid at the falling edge of clock.

VDD

Positive power supply, 2.0V~5.5V for normal operation

VSS

Negative power supply, ground

Approximate internal connection circuits

HT9302 Series

Rev. 1.20

September 30, 2002

N M O S O U T

D D

C M O S I N / O U T

C M O S I N

P u l l - l o w

C M O S I N

P u l l - h i g h

C M O S I N

O S C I L L A T O R

X 1

X 2

1 0 M W

2 0 p .

1 0 p .

C M O S O U T

D D

Absolute Maximum Ratings

Supply Voltage ...........................................

-0.3V to 6V

Storage Temperature ...........................

-50°C to 125°C

Input Voltage .............................. V

-0.3 to V

+0.3V

Operating Temperature ..........................

-20°C to 75°C

Note: These are stress ratings only. Stresses exceeding the range specified under

²Absolute Maximum Ratings² may

cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil-
ity.

Electrical Characteristics

OSC

=3.5795MHz, Ta=25

°C

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Conditions

Operating Voltage

5.5

Operating Current

2.5V

Pulse

Off-hook
Keypad entry
No load

0.2

Tone

0.6

STB

Standby Current

On-hook, no load
No entry

Memory Retention Voltage

5.5

Memory Retention Current

On-hook

0.1

0.2

Input Low Voltage

0.2V

Input High Voltage

0.8V

XMO

XMUTE Leakage Current

XMUTE

=12V

No entry

OLXM

XMUTE Sink Current

2.5V V

XMUTE

=0.5V

HKS

HKS Pin Input Current

2.5V V

HKS

=2.5V

0.1

HFI

HFI Pull-low Resistance

2.5V V

HFI

=2.5V

200

HDI

HDI Pull-high Resistance

2.5V V

HDI

=0V

200

OH1

Keypad Pin Source Current

2.5V V

=0V

-4

OL1

Keypad Pin Sink Current

2.5V V

=2.5V

200

400

OH2

HFO Pin Source Current

2.5V V

=2V

-1

OL2

HFO Pin Sink Current

2.5V V

=0.5V

OH3

HDO Pin Source Current

2.5V V

=2V

-1

OL3

HDO Pin Sink Current

2.5V V

=0.5V

Pause Time After Flash

Control key

0.2

Digit key

One-key Redialing Pause Time

One-key redialing

Key-in Debounce Time

BRK

Break Time for One-key Redialing

One-key redialing

1.2

OSC

System Frequency

Crystal=3.5795MHz

3.5759

3.5795

3.5831

MHz

HT9302 Series

Rev. 1.20

September 30, 2002

Pulse Mode Electrical Characteristics

OSC

=3.5795MHz, Ta=25

°C

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Conditions

POH

PO Output Source Current 2.5V V

=2V

-0.2

POL

PO Output Sink Current

2.5V V

=0.5V

0.2

0.6

Pulse Rate

MODE pin is connected to V

pps

MODE pin is opened

M/B

Make/Break Ratio

A resistor is linked between R2
and C1

33:66

No resistor is linked between
R2 and C1

40:60

PDP

Pre-digit-pause Time

M/B ratio=40:60

40 (10pps)
20 (20pps)

M/B ratio=33:66

33 (10pps)
17 (20pps)

IDP

Inter-digit-pause Time

Pulse rate=10pps

800

Pulse rate=20pps

500

Pulse Make Duration

A resistor is linked between R2
and C1

33 (10pps)
17 (20pps)

No resistor is linked between
R2 and C1

40 (10pps)
20 (20pps)

Pulse Break Duration

A resistor is linked between R2
and C1

66 (10pps)
33 (20pps)

No resistor is linked between
R2 and C1

60 (10pps)
30 (20pps)

Tone Mode Electrical Characteristics

OSC

=3.5795MHz, Ta=25

°C

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

Conditions

TDC

DTMF Output DC Level

0.45V

0.7V

TOL

DTMF Sink Current

2.5V V

DTMF

=0.5V

0.1

TAC

DTMF Output AC Level

¾ Row group, R

=5k

0.12

0.155

0.18

Vrms

DTMF Output Load

2.5V THD

£-23dB

Column Pre-emphasis

2.5V Row group=0dB

THD

Tone Signal Distortion

2.5V R

=5k

-30

-23

TMIN

Minimum Tone Duration

¾ Auto-redial

Others

82.5

9302G

100

ITPM

Minimum Inter-tone Pause

¾ Auto-redial

Others

85.5

9302G

106

THD (Distortion) (dB) = 20 log

(

)

Vn /

Vi, Vh: Row group and column group signals

V1, V2, ... Vn: Harmonic signals (BW=300Hz~3500Hz)

HT9302 Series

Rev. 1.20

September 30, 2002

HT9302 Series

Rev. 1.20

September 30, 2002

Functional Description

Keyboard matrix

C1~C4 and R1~R4 form a keyboard matrix. Together

with a standard 4

´4 keyboard, the keyboard matrix is

used for dialing entries. In addition, the keyboard ma-
trix provides resistor option for different dialing specifi-
cation selections. The keyboard arrangement for each of
the HT9302 series are shown in the Keyboard Informa-
tion.

Tone frequency

Tone

Name

Output Frequency (Hz)

% Error

Specified

Actual

697

699

+0.29%

770

766

-0.52%

852

847

-0.59%

941

948

+0.74%

1209

1215

+0.50%

1336

1332

-0.30%

1477

1472

-0.34%

Note: % Error does not contain the crystal frequency

drift

Dialing specification selection

By means of adding resistors on the keyboard matrix
pins, various dialing specifications can be selected. The
allowable option resistor connections are shown.

All the resistors are 330k

W. The resistor option functions

and the default specifications (without option resistors)
are listed below.

Option

Resistor

Option

Function

Default

(No Resistor)

K12

Make/Break Ratio
Selection

40:60

K13

Flash Function and
Flash Time Selection

Flash=control function
Flash time=600ms

K14

K21

Pause & P

®T

Duration Selection

=3.6s

®T

=3.6s

K31

Pulse Number
Selection

K41

M/B ratio selection table

K12

M/B Ratio (%)

40:60

Yes

33.3:66.6

Flash function/time (duration) selection table

K13

K14

Flash

Function

Flash

Time (t

)

Control

600ms

Yes

Digit

600ms

Yes

Digit

98ms

Yes

Digit

300ms

Pause and P

®T duration selection table

K21

(sec)

®T

(sec)

3.6

Yes

Pulse number selection table

This table shows pulse number selections for
HT9302x.

K31

K41

Pulse Number

Yes

N+1

Yes

-N

Yes

HT9302G has different selection method listed in the
table below.

K31

Pulse Number

Yes

10-N

C 4

C 3

C 2

C 1

R 4

R 3

R 1

R 2

K 2 1

K 3 1

K 4 1

K 1 2

K 1 3

K 1 4

HT9302 Series

Rev. 1.20

September 30, 2002

Pulse number table

Keypad

Output Pulse Number

Digit Key

Normal N

New

Zealand

(10

-N)

Sweden/

Denmark

(N+1)

*/T

®T

Ignored

Hand-free function operation

Hand-free function execution
When HFO is low, a rising edge triggers the HFI, en-
abling the Hand-free function (HFO becomes high).

Reset Hand-free function
When HFO is high, the Hand-free function is enabled
and can be reset by:

Off-hook

Applying a rising edge to HFI

Changing the HDO pin from low to high

Hand-free function table

Hold-line function operation

Hold-line function execution
When HDO is low, a falling edge triggers the HDI, en-
abling the Hold-line function (HDO becomes high).
The XMUTE remains low when HDO is high.

Reset Hold-line function
When HDO is high, the Hold-line function is enabled
and can be reset by:

Off-hook

Applying a falling edge to HDI

Changing the HFO pin from low to high

Hold-line function table

DOUT BCD code

When dialing, the corresponding 4-bit BCD codes are
serially presented on DOUT from MSB to LSB. The data
of DOUT is valid at the falling edge of the CLOCK pin.
The following table lists the BCD codes corresponding
to the keyboard input.

Key-In

BCD Code

Key-In

BCD Code

0001

1000

0010

1001

0011

1010

0100

*/T

1101

0101

1100

0110

1011

0111

1110

C u r r e n t S t a t e

I n p u t

N e x t S t a t e

H K S

H . O

H D O

H . I

H K S

A n

H . O

A n

H D O

A n

H D I

H :

L :

L o g i c H I G H
L o g i c L O W

X :

A n :

D o n ' t c a r e
U n c h a n g e d

:
:

R i s i n g e d g e
. a l l i n g e d g e

C u r r e n t S t a t e

I n p u t

N e x t S t a t e

H K S

H D O

H . O

H D I

H K S

A n

H D O

A n

H . O

A n

H . I

H :

L :

L o g i c H I G H
L o g i c L O W

X :

A n :

D o n ' t c a r e
U n c h a n g e d

:
:

R i s i n g e d g e
. a l l i n g e d g e

HT9302 Series

Rev. 1.20

September 30, 2002

LOCK function

The function aims to detect locked dialing number to
prevent a long distance call. The dialing output of the
chip is disabled if the first input key after on-off-hook is
the locked number when the lock function is enabled.
The lock function selection is listed below.

HT9302x version

LOCK Pin

Function

OPEN

Normal dialing (no lock)

VDD

²0, 9² is inhibited

VSS

²0² is inhibited

Key definition

0,1,2,3,4,5,6,7,8,9 keys
These are dialing number input keys for both the pulse
mode and the tone mode operations.

*/T
This key executes the P

®T function and waits a t

®T

duration in the pulse mode. On the other hand, the

*/T

key executes the

* function in the tone mode.

#
This is a dialing signal key for the tone mode only, no
response in the pulse mode.

SA
Pressing this key can save the preceding dialing tele-
phone numbers. The saved number is redialed if it is
pressed again. SA will also redial the saved number if
it is the first key pressed at the off-hook state. During
the dialing signal transmission, the SA key is inhibited.

The flash key can be selected as a digit or a control key
by the option resistors R

K13

& R

K14

. Pressing the flash

key will force the PO pin to be

²low² for the t

duration

and is then followed by t

(sec). t

can also be selected

by R

K13

, R

K14

P
Pause key. The execution of the pause key pauses
the output for the t

duration. t

can be selected by

K21

R
Redial key. Executes redialing as well as one-key re-
dial function.

ST
This key can store lock number with personal code in
IDD lock operation.

R/P
Redial and pause function key. If it is pressed as the
first key after off-hook, this key executes the redial
function. Otherwise, it works as the pause key.

Keyboard operation

The following operations are described under an on-off- hook or on-hook condition with the hand-free active condition.

HT9302 Series

Rev. 1.20

September 30, 2002

K e y b o a r d i n p u t : D 1 D 2 . . . D n

- P u l s e m o d e

( a ) w i t h o u t * / T

D i a l i n g o u t p u t : D 1 D 2 . . . D n
R M : D 1 D 2 . . . D n
S A M : U n c h a n g e d

( b ) w i t h * / T

D i a l i n g o u t p u t : D 1 D 2 . . . D n t

P ® T

D n + 1 . . . D m

R M : D 1 D 2 . . . D n * / T D n + 1 . . . D m
S A M : U n c h a n g e d

T o n e

P u l s e

· N o r m a l d i a l i n g

K e y b o a r d i n p u t : D 1 D 2 . . . D n * / T D n + 1 . . .

D m

( a ) w i t h o u t * / T

D i a l i n g o u t p u t : D 1 D 2 . . . D n
R M : D 1 D 2 . . . D n
S A M : U n c h a n g e d

( b ) w i t h * / T

D i a l i n g o u t p u t : D 1 D 2 . . . D n * D n + 1 . . . D m
R M : D 1 D 2 . . . D n * D n + 1 . . . D m
S A M : U n c h a n g e d

- T o n e m o d e

( a ) w i t h o u t * / T

D i a l i n g o u t p u t : D 1 D 2 . . . D n
R M : U n c h a n g e d
S A M : U n c h a n g e d

R M c o n t e n t : D 1 D 2 . . . D n

( b ) w i t h * / T

D i a l i n g o u t p u t : D 1 D 2 . . . D n t

P ® T

D n + 1 . . . D m

R M : U n c h a n g e d
S A M : U n c h a n g e d

R M c o n t e n t : D 1 D 2 . . . D n * / T D n + 1 . . . D m

D i a l i n g o u t p u t : D 1 D 2 . . . D n
R M : U n c h a n g e d
S A M : U n c h a n g e d

R M c o n t e n t : D 1 D 2 . . . D n

( b ) w i t h * / T

D i a l i n g o u t p u t : D 1 D 2 . . . D n * D n + 1 . . . D m
R M : U n c h a n g e d
S A M : U n c h a n g e d

R M c o n t e n t : D 1 D 2 . . . D n * / T D n + 1 . . . D m

- P u l s e m o d e

- T o n e m o d e

P u l s e

T o n e

· R e d i a l

K e y b o a r d i n p u t : D 1 D 2 . . . D n * / T D n + 1 . . .

D m

( a ) w i t h o u t * / T

K e y b o a r d i n p u t : D 1 D 2 . . . D n

K e y b o a r d i n p u t : [ R o r R / P ]

N o t e : T h e m a x i m u m c a p a c i t y o f t h e R M m e m o r y i s 3 2 d i g i t s . W h e n m o r e t h a n 3 2 d i g i t s a r e e n t e r e d ,

t h e s i g n a l i s t r a n s m i t t e d b u t t h e r e d i a l f u n c t i o n i s i n h i b i t e d .

HT9302 Series

Rev. 1.20

September 30, 2002

D m

S A

K e y b o a r d i n p u t : D 1 D 2 . . . D n * / T D n + 1 . . .

D m

K e y b o a r d i n p u t : D 1 D 2 . . . D n * / T D n + 1 . . .

K e y b o a r d i n p u t : D 1 D 2 . . . D n R

( a ) w i t h o u t * / T

D i a l i n g o u t p u t : D 1 D 2 . . . D n t

B R K

R P

R M : D 1 D 2 . . . D n
S A M : U n c h a n g e d

( b ) w i t h * / T

R M : D 1 D 2 . . . D n * / T D n + 1 . . . D m
S A M : U n c h a n g e d

( a ) w i t h o u t * / T

R M : D 1 D 2 . . . D n
S A M : U n c h a n g e d

( b ) w i t h * / T

- T o n e m o d e

- P u l s e m o d e

P u l s e

B R K

R P

D 1 D 2 . . . D n t

P ® T

P u l s e

D i a l i n g o u t p u t : D 1 D 2 . . . D n * D n + 1 . . . D m

R M : D 1 D 2 . . . D n * D n + 1 . . . D m
S A M : U n c h a n g e d

B R K

R P

D 1 D 2 . . . D n * D n + 1

. . . D m

T o n e

D i a l i n g o u t p u t : D 1 D 2 . . . D n t

P ® T

D n + 1 . . . D m

T o n e

· O n e - k e y r e d i a l

( a ) w i t h o u t * / T

D i a l i n g o u t p u t : D 1 D 2 . . . D n
R M : D 1 D 2 . . . D n
S A M : D 1 D 2 . . . D n

( b ) w i t h * / T

R M : D 1 D 2 . . . D n * / T D n + 1 . . . D m
S A M : D 1 D 2 . . . D n * / T D n + 1 . . . D m

( a ) w i t h o u t * / T

D i a l i n g o u t p u t : D 1 D 2 . . . D n
R M : D 1 D 2 . . . D n
S A M : D 1 D 2 . . . D n

( b ) w i t h * / T

D i a l i n g o u t p u t : D 1 D 2 . . . D n * D n + 1 . . . D m
R M : D 1 D 2 . . . D n * D n + 1 . . . D m
S A M : D 1 D 2 . . . D n * D n + 1 . . . D m

- P u l s e m o d e

- T o n e m o d e

D i a l i n g o u t p u t : D 1 D 2 . . . D n t

P ® T

D n + 1 . . . D m

T o n e

P u l s e

· S A c o p y

D 1 D 2 . . . D n

D i a l i n g o u t p u t : D 1 D 2 . . . D n t

B R K

R P

D 1 D 2

. . . D n

D n + 1 . . . D m

K e y b o a r d i n p u t : D 1 D 2 . . . D n R

D m

K e y b o a r d i n p u t : D 1 D 2 . . . D n * / T D n + 1 . . .

K e y b o a r d i n p u t : D 1 D 2 . . . D n S A

D m

S A

K e y b o a r d i n p u t : D 1 D 2 . . . D n * / T D n + 1 . . .

N o t e : T h e m a x i m u m c a p a c i t y o f t h e R M m e m o r y i s 3 2 d i g i t s . W h e n m o r e t h a n 3 2 d i g i t s p l u s t h e " S A " k e y

a r e e n t e r e d , t h e S A V E f u n c t i o n w i l l n o t b e e x e c u t e d , a n d a l l t h e e x i s t i n g d a t a i n t h e s a v e m e m o r y

w i l l n o t b e c h a n g e d .

N o t e : I f t h e d i a l i n g n u m b e r e x c e e d s 3 2 d i g i t s , r e d i a l i n g i s i n h i b i t e d a n d P O = V D D

HT9302 Series

Rev. 1.20

September 30, 2002

K e y b o a r d i n p u t : D 1 D 2 . . . D n . D n + 1 . . .

D m

( a ) w i t h o u t * / T

D i a l i n g o u t p u t : D 1 D 2 . . . D n
R M : U n c h a n g e d
S A M : U n c h a n g e d

( b ) w i t h * / T

R M : U n c h a n g e d
S A M : U n c h a n g e d

( a ) w i t h o u t * / T

D i a l i n g o u t p u t : D 1 D 2 . . . D n
R M : U n c h a n g e d
S A M : U n c h a n g e d

( b ) w i t h * / T

D i a l i n g o u t p u t : D 1 D 2 . . . D n * D n + 1 . . . D m
R M : U n c h a n g e d
S A M : U n c h a n g e d

S A M c o n t e n t : D 1 D 2 . . . D n

S A M c o n t e n t : D 1 D 2 . . . D n * / T D n + 1 . . . D m

S A M c o n t e n t : D 1 D 2 . . . D n

S A M c o n t e n t : D 1 D 2 . . . D n * D n + 1 . . . D m

- P u l s e m o d e

- T o n e m o d e

D i a l i n g o u t p u t : D 1 D 2 . . . D n t

P ® T

D n + 1 . . . D m

T o n e

P u l s e

· S A d i a l i n g

K e y b o a r d i n p u t : S A

R M : D 1 D 2 . . . D n
S A M : U n c h a n g e d

- . l a s h a s a d i g i t a l k e y

- . l a s h a s a c o n t r o l k e y

( a ) T h e i n t e r v e n i e n t k e y

R M : U n c h a n g e d
S A M : U n c h a n g e d

D i a l i n g o u t p u t : t

. P

D 1 D 2 . . . D n

K e y b o a r d i n p u t : . D 1 D 2 . . . D n

( b ) T h e f i r s t k e y

· . l a s h

D i a l i n g o u t p u t : D 1 D 2 . . . D n t

. P

D n + 1 . . .

D m

R M : D n + 1 . . . D m
S A M : U n c h a n g e d

D i a l i n g o u t p u t : D 1 D 2 . . . D n T

. P

D n + 1 . . .

D m

N o t e : T

: b r e a k a f l a s h t i m e

K e y b o a r d i n p u t : D 1 D 2 . . . D n . D n + 1 . . .

D m

D i a l i n g o u t p u t : D 1 D 2 . . . D n t

D n + 1 . . . D m

R M : D 1 D 2 . . . D n P D n + 1 . . . D m
S A M : U n c h a n g e d

K e y b o a r d i n p u t : D 1 D 2 . . . D n P D n + 1 . . . D m

· P a u s e

· N o t e

R M : R e d i a l m e m o r y

S A M : S a v e d i a l i n g m e m o r y

D 1 D 2 . . . D n : 0 ~ 9

D n + 1 . . . D m : 0 ~ 9 , * , #

Application Circuits

Application circuit 1

HT9302 Series

Rev. 1.20

September 30, 2002

T
E

1
0
p
p
s

2
0
p
p
s

T
o
n
e

3
.
5
8
M

r
e
s
o
n
a
t
o
r

1
5
0
W

1
4

1
3

5
.
1
V

1
N

4
1
4
8

1
N

4
1
4
8

4
2

9
2

2
2
M

T
i
p

i
n
g

1
A

b
r
i
d
g
e

T
M

1
5

1
6

1
7

1
8

k
R

1
m
.

T
W

1
1

1
0

1
2

*

R

k

f
o
r

d
i
a
l
i
n
g

s
i
g
n
a
l

o
p
t
i
o
n

(
R

e
f
e
r

t
o

t
h
e

f
u
n
c
t
i
o
n
a
l

d
e
s
c
r
i
p
t
i
o
n
)

*

U

n
s
p
e
c
i
f
i
e
d

t
r
a
n
s
i
s
t
o
r
s

a
r
e

o
f

8
0
5
0

t
y
p
e

*

A

.

c
a
p
a
c
i
t
o
r

b
e
t
w

e
e
n

X

T
E

a
n
d

V

(
G

)

i
s

r
e
c
o
m

e
n
d
e
d

*
/
T

L
O

0
,

9

n
o

l
o
c
k

1
0
p
.

3
9
p
.

1
m
.

1
.
5
k
W

2
2
0
k
W

1
0
0
k
W

2
7
0
k
W

1
0
0
m
.

0
.
1
m
.

2
.
2
k
W

4
7
k
W

3
.
3
k
W

1
0
0
k
W

f
f
-
h
o
o
k

n
-
h
o
o
k

T
9
3
0
2
A

Application circuit 2

HT9302 Series

Rev. 1.20

September 30, 2002

1
5
0
W

1
0
0
m
.

5
.
1
V

o
l
d

1
N

4
1
4
8

1
N

4
1
4
8

1
N

4
1
4
8

1
N

4
1
4
8

x

4

1
m
.

1
6
V

1
N

4
1
4
8

a
n
d
-
f
r
e
e

4
2

1
0
m
.

5
0
V

9
2

2
2
M

T
i
p

i
n
g

1
A

b
r
i
d
g
e

T
E

1
7

1
0

T
M

.
O

1
8

1
9

2
0

2
1

k
R

1
m
.

1
5

.
I

1
1

2
2

1
3

1
4

T
W

*
/
T

1
6

1
2

1
0
p
p
s

2
0
p
p
s

T
o
n
e

3
.
5
8
M

r
e
s
o
n
a
t
o
r

L
O

0
,

9

n
o

l
o
c
k

1
0
p
.

*

R

k

f
o
r

d
i
a
l
i
n
g

s
i
g
n
a
l

o
p
t
i
o
n

(
R

e
f
e
r

t
o

t
h
e

f
u
n
c
t
i
o
n
a
l

d
e
s
c
r
i
p
t
i
o
n
)

*

U

n
s
p
e
c
i
f
i
e
d

t
r
a
n
s
i
s
t
o
r
s

a
r
e

o
f

8
0
5
0

t
y
p
e

*

A

.

c
a
p
a
c
i
t
o
r

b
e
t
w

e
e
n

X

T
E

a
n
d

V

(
G

)

i
s

r
e
c
o
m

e
n
d
e
d

1
0
p
.

3
9
p
.

1
m
.

0
.
1
m
.

1
.
5
k
W

4
7
k
W

1
0
0
k
W

2
7
0
k
W

2
2
0
k
W

2
.
2
k
W

1
0
0
k
W

2
2
0
k
W

2
2
k
W

0
.
1
m
.

3
3
0
k
W

2
2
0
k
W

1
0
0
k
W

3
3
k
W

3
.
3
k
W

4
7
k
W

0
.
0
2
m
.

1
0
k
W

f
f
-
h
o
o
k

n
-
h
o
o
k

T
9
3
0
2
B

Application circuit 3

HT9302 Series

Rev. 1.20

September 30, 2002

T
E

3
.
5
8
M

r
e
s
o
n
a
t
o
r

1
5
0
W

1
5

5
.
1
V

1
N

4
1
4
8

1
N

4
1
4
8

4
2

9
2

2
2
M

T
i
p

i
n
g

1
A

b
r
i
d
g
e

T
M

1
7

1
8

1
9

2
0

k
R

1
m
.

1
3

1
2

1
4

1
0

L
O

1
1

T
W

T
1
6
X

L
C

I
V

(
s
e
e

H

T
1
6
X

d
a
t
a
)

*
/
T

1
0
p
p
s

2
0
p
p
s

T
o
n
e

1
6

L
O

0
,

9

n
o

l
o
c
k

1
0
p
.

*

R

k

f
o
r

d
i
a
l
i
n
g

s
i
g
n
a
l

o
p
t
i
o
n

(
R

e
f
e
r

t
o

t
h
e

f
u
n
c
t
i
o
n
a
l

d
e
s
c
r
i
p
t
i
o
n
)

*

U

n
s
p
e
c
i
f
i
e
d

t
r
a
n
s
i
s
t
o
r
s

a
r
e

o
f

8
0
5
0

t
y
p
e

*

A

.

c
a
p
a
c
i
t
o
r

b
e
t
w

e
e
n

X

T
E

a
n
d

V

(
G

)

i
s

r
e
c
o
m

e
n
d
e
d

1
0
p
.

3
9
p
.

1
m
.

1
.
5
k
W

1
0
0
k
W

2
2
0
k
W

1
0
0
k
W

1
0
0
m
.

2
7
0
k
W

2
.
2
k
W

0
.
1
m
.

3
.
3
k
W

4
7
k
W

1
0
0
k
W

f
f
-
h
o
o
k

n
-
h
o
o
k

T
9
3
0
2
C

Application circuit 4

HT9302 Series

Rev. 1.20

September 30, 2002

*
/
T

1
5
0
W

5
.
1
V

o
l
d

1
N

4
1
4
8

1
N

4
1
4
8

1
N

4
1
4
8

1
N

4
1
4
8

x

4

1
m
.

1
6
V

1
N

4
1
4
8

a
n
d
-
f
r
e
e

4
2

1
0
m
.

5
0
V

9
2

2
2
M

T
i
p

i
n
g

1
A

b
r
i
d
g
e

T
E

2
0

2
1

2
2

2
3

k
R

1
m
.

1
7

.
I

1
1

2
4

1
5

1
6

T
W

1
8

1
4

1
2

4
7
k
W

1
N

4
1
4
8

T
M

.
O

T
1
6
X

L
C

I
V

(
s
e
e

H

T
1
6
X

d
a
t
a
)

1
0
p
p
s

2
0
p
p
s

T
o
n
e

3
.
5
8
M

r
e
s
o
n
a
t
o
r

1
9

1
0

L
O

1
3

L
O

0
,

9

n
o

l
o
c
k

1
0
p
.

*

R

k

f
o
r

d
i
a
l
i
n
g

s
i
g
n
a
l

o
p
t
i
o
n

(
R

e
f
e
r

t
o

t
h
e

f
u
n
c
t
i
o
n
a
l

d
e
s
c
r
i
p
t
i
o
n
)

*

U

n
s
p
e
c
i
f
i
e
d

t
r
a
n
s
i
s
t
o
r
s

a
r
e

o
f

8
0
5
0

t
y
p
e

*

A

.

c
a
p
a
c
i
t
o
r

b
e
t
w

e
e
n

X

T
E

a
n
d

V

(
G

)

i
s

r
e
c
o
m

e
n
d
e
d

1
0
p
.

3
9
p
.

1
m
.

4
7
k
W

1
.
5
k
W

1
0
0
k
W

2
2
0
k
W

2
7
0
k
W

2
.
2
k
W

0
.
1
m
.

1
0
0
m
.

2
2
k
W

0
.
1
m
.

1
0
0
k
W

2
2
0
k
W

3
3
k
W

1
0
k
W

3
3
0
k
W

1
0
0
k
W

4
7
k
W

3
.
3
k
W

0
.
0
2
m
.

1
0
0
k
W

f
f
-
h
o
o
k

n
-
h
o
o
k

T
9
3
0
2
D

Application circuit 5

HT9302 Series

Rev. 1.20

September 30, 2002

T
E

1
0
p
p
s

2
0
p
p
s

T
o
n
e

3
.
5
8
M

r
e
s
o
n
a
t
o
r

1
5
0
W

1
2

1
1

5
.
1
V

1
N

4
1
4
8

1
N

4
1
4
8

4
2

9
2

2
2
M

T
i
p

i
n
g

1
A

b
r
i
d
g
e

1
0
p
.

T
M

1
3

1
4

1
5

1
6

k
R

1
m
.

1
0

T
W

*
/
T

*

R

k

f
o
r

d
i
a
l
i
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HT9302 Series

Rev. 1.20

September 30, 2002

Ó 2002 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as-
sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek reserves the right to alter its products without prior notification. For the most
up-to-date information, please visit our web site at http://www.holtek.com.tw.

Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw

Holtek Semiconductor Inc. (Sales Office)
11F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)

Holtek Semiconductor (Shanghai) Inc.
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn

Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657

Holmate Semiconductor, Inc.
48531 Warm Springs Boulevard, Suite 413, Fremont, CA 94539
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HT9302A

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HT9302A

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HT9302A