HI-6010

The HI-6010 is a CMOS integrated circuit designed to
interface the avionics data bus standard ARINC 429 to an
8 bit port. It contains one receiver and one transmitter.
They operate independently except for the self test option
and the parity option.

The receiver demands that the

incoming data meet the standard protocol and the
transmitter outputs a standard protocol stream.

The HI-6010 provides flexible options for interfacing to the
user system. The controlling processor can operate both
the receiver and transmitter either by using hard wired
flags and gates at the pins or by using software reads and
writes of the Status Register and Control Register or a
combination thereof.

The chip is programmable to operate with single 8 bit
bytes requiring "on the fly transmitter loading and receiver
downloading" or to operate in 32 bit "extended buffer"
mode. In addition there is an option to use automatic label
recognition after loading 8 possible labels for comparison.
Parity and self test are also software programmable.
Master Reset is activated only by taking theMRpinhigh.

Two clock inputs allow independent selection of the data
rates of the transmitter and receiver. Each must be 4X the
desired ARINC 429 frequency.

Error flags are generated for transmitter underwrites and
for receiver data framing miscues, parity errors, and buffer
overwrites.

The HI-6010 is a 5 volt chip that will require data transla-
tion from and to the ARINC bus. The HI-8482 and HI-8588
line receivers are available for the receiver side and the
HI-318X, HI-838X and HI-858X line drivers are available
for the transmitter side. The HI-8590 is also available with
a line driver and a line receiver in a single 16-pin thermally
enhanced ESOIC package.

VDD = 5.0 VOLTS �5%

VSS = 0.0 VOLTS

GENERAL DESCRIPTION

ARINC 429 protocol controller with interface to
an 8 bit bus

Automatic label recognition option

8 bit or 32 bit buffering option

Self test and parity options

CMOS / TTL logic pins

Plastic and ceramic package options - surface
mount or DIP

Military processing available

Avionics Data Communication

Serial to Parallel Conversion

Parallel to Serial Conversion

FEATURES

PIN CONFIGURATION

(Top View)

28
27 C/
26
25
24 D7
23 D6
22 D5
21 D4
20 D3
19 D2
18 D1
17 D0
16 RXD1
15 V

CS
WE

WEF 2

TXC 4
HFS 5

MR 6

TXE 7

RXRDY 8

TXRDY 9

TXD0 10
TXD1 11

RXC 12

FCR 13

RXD0 14

CTS

Pin numbers apply for plastic and ceramic DIP and
for plastic PLCC. Consult factory for pin out of 48
lead ceramic leadless chip carrier.

HOLT INTEGRATED CIRCUITS

(DS6010 Rev. A)

01/01

4-3

PIN

SYMBOL

FUNCTION

DESCRIPTION

POWER

0.0 Volts

WEF

OUTPUT

Error indication if high. Status register must be read to determine specific error.

INPUT

Enables data transmission when low.

TXC

INPUT

Source clock for data transmission. 4 times bit rate.

HFS

INPUT

Hardware feature select.

INPUT

Master reset, active high.

TXE

OUTPUT

Low when transmission in progress.

RXRDY

OUTPUT

High when data of received word is available.

TXRDY

OUTPUT

High when data of a transmitted word may be input.

TXD0

OUTPUT

"Zeroes" data output of transmitter.

TXD1

OUTPUT

"Ones" data output of transmitter.

RXC

INPUT

Source clock for data reception. 4 times bit rate.

FCR

OUTPUT

First character received flag.

RXD0

INPUT

"Zeroes" data input to receiver.

POWER

5 Volts �5%

RXD1

INPUT

"Ones" data input to receiver.

I / O

Data bus

I / O

Data bus

I / O

Data bus

I / O

Data bus

I / O

Data bus

I / O

Data bus

I / O

Data bus

I / O

Data bus

INPUT

8 bit data bus input control active low.

INPUT

Chip select, active low.

INPUT

High for control or status register operations, low for data

INPUT

8 bit data bus output control, active low.

CTS

HI-6010

The receiver logic is independent of the transmitter except in
the following ways:

Self Test

Parity Option

In self test, the transmitter outputs route to the receiver inputs
internally ignoring the external inputs. Also in self test, the
external receiver clock is replaced with the transmitter clock.

The parity option affects both the receiver and transmitter.
Either both are operational or neither.

WEF is an error indicator.

It goes high for a transmitter

"underwrite" (failure to keep up with byte loading) and pin 2

HARDWARE CONTROL OF THE RECEIVER

PIN 2 - WEF

goes high for any one of three receiver errors. The status
register will show which of the three errors occurred:

SR3

Received a parity error

SR4

Data Overwritten

SR5

Receiving sequence error

The possible Receiver sequence errors are:

1. RXD0 and RXD1 simultaneously a one.
2. Less than 32 bits before 3 nulls.
3. More than 32 bits.

There are no errors flagged for labels received that don't
match stored labels when in the label recognition mode.
Errors are cleared by MR or by reading the Status Register.

This pin, along with the control register, sets up the
functioning (e.g. modes) of the chip.

If HFS is low, the

Status Register Bit

Error

PIN 5 - HFS and the CONTROL REGISTER

HOLT INTEGRATED CIRCUITS

4-4

COMMUNICATING WITH THE CONTROL AND
STATUS REGISTERS

LABEL RECOGNITION OPTION

LOADING LABELS

READING LABELS

Pin 27, C/ , must be high to read the status register or write
the control register.

Reading the status register resets

errors. There is no provision to read the control register.

Pin 5 must be high if label recognition is selected in either the
8 or 32 bit modes and all eight label buffers must be written
using redundant labels, if necessary.

The chip compares the incoming label to the stored labels. If
a match is found, the data is processed. If a match is not
found, no indicators of receiving ARINC data are presented.

After the write that changes CR7 from 0 to 1, the next 8 writes
of data (C/

is a zero for data) will load the label registers.

Labels must be loaded whenever pin 5 goes from low to
high.

After the write that changes CR1 from 0 to 1, the next 8 data
reads are labels.

PIN 6 - MR

PIN 8 - RXRDY

PIN 12 - RXC

PIN 13 - FCR

When MR is a 1, the control word is set to 0X10 0101 (CR7 -
CR0).

For the receiver this sets up 8 bit mode with the

receiver and parity enabled. MR also initializes the registers
and logic. The first ARINC reception will only occur

word gap.

In 8 bit mode, this pin goes high whenever 8 bits are received
without error. In 32 bit mode this pin goes high after all 32 bits
are received with no error. This flag may be inhibited for one
ARINC word if CR3 is programmed to 1. This flag is also
inhibited in label recognition if the incoming ARINC label does
notmatch one of the stored 8 labels.

This pin must have a clock applied that is 4X the desired
receive frequency.

In 8 bit mode, this pin flags the first character (byte) received.
In 32 bit mode, this pin goes high for a valid 32 bit word. The
pin is not affected by CR3 programming.

after

receiver is not programmable to the 32 bit "extended buffer"
mode nor to the label recognition mode.

Affecting the

receiver:

PIN 14 - RXD0 and PIN 16 - RXD1

These pins must be 5 volt logic levels.

There must be a

translator between the

ARINC bus and these inputs.

Typically a receiver chip, such as the HI-8482 or HI-8588
is inserted between the ARINC bus and the logic chips.
RXD0 is looking for a high level for zero inputs and RXD1 is
looking for a high level for one inputs. When both inputs are
low this is referred to as the Null state.

By writing to the Control Register and reading the Status
Register the controlling processor can operate the receiver
without hardware interrupts.

The Control Register in

combination with the wiring of pin 5 was explained above.
The Status Register bits pertaining to the receiver are
explained below:

SOFTWARE CONTROL OF THE RECEIVER

* CR3 will be automatically reset to 0 after being programmed
to a 1 at the completion of an ARINC word reception. This
allows a software label recognition different from the automatic
option available.

CONTROL PROGRAM PIN 5
BIT NAME

VALUE

OPERATION

CR1

No action

Next 8 data read cycles will read
stored labels. One time only sequence
on each transiton of CR1 to a 1.

CR2

Receiver is disabled

Receiver is enabled

CR3*

RXRDY goes high normally

Blocks RXRDY for one ARINC word

CR4

Self test disabled

Self test enabled

CR5

No parity errors enabled and 32nd
bit is data

Parity error flag enabled

32 bit "extended mode" enabled and
parity enabled.

8 bit "one byte at a time" mode and
parity enabled.

CR7

Label recognition not programmable

Label recognition disabled

Label recognition enabled

SR1

No receiver data

Receiver data ready

SR3

No parity error

Parity error - Parity was even

SR4

Receiver data not overwritten

Receiver data was overwritten

SR5

Receiver data received without framing error

Framing error - Did not receive exactly 32
good bits

SR6

Did not receive first byte

Received first byte - Same flag as pin 13

STATUS BIT VALUE

MEANING

HI-6010

HOLT INTEGRATED CIRCUITS

4-5

The transmitter logic is independent of the receiver except in
the following ways:

Self Test

Parity Option

In self test the transmitter outputs route to the receiver inputs
internally and the TXD0 and TXD1 outputs are inhibited.

When parity is enabled, both the receiver and transmitter are
affected. Odd parity is automatically generated in the 32nd
bit if this option is selected.

This output goes high for 1 transmitter error and 3 receiver
errors. To determine which error is being flagged, read the
Status Register. Reading the Status Register also clears the
error flag. The transmitter will not function until the error is
cleared. It can also be cleared by MR going high.

The only possible transmitter error is generated when running
in 8 bit mode. For the transmitter this means loading the last 3
bytes while the transmission is in progress. Failure to load a
byte before the previous byte's 8th bit is transmitted will
generate the error, indicated by status bit SR7 set to a 1.

This pin is a hardware gate for transmissions.

If the

transmitter buffer is loaded and Control Register bit CR0 is a
one, the only inhibit of the transmitter would be for

to be a

one. When taken low, transmission of an ARINC word is
enabled. It may be pulsed to release each transmitted word.

The data rate of transmission is controlled by this pin. This
clock must be 4X the desired date rate.

This pin along with the Control Register sets the functioning of
the chip. For the transmitter:

HARDWARE CONTROL OF THE TRANSMITTER

PIN 2 - WEF

PIN 3 -

PIN 4 - TXC

PIN 5 - HFS and the CONTROL REGISTER

CTS

CTS

PIN 6 - MR

PIN 7 - TXE

PIN 9 - TXRDY

PIN 10 - TXD0 and PIN 11 - TXD1

The chip is initialized whenever this pin goes high.

The

Control Register is set to 0X10 0101 (CR7 - CR0). For the
transmitter this sets up 8 bit mode with the transmitter
enabled.

Whenever a transmission begins, this pin goes low and
returns high after the transmission is complete.

Whenever TXRDY is a one, data may be written into the
transmitter buffer. In 8 bit "one byte at a time" mode, this pin
may bemonitored to indicate when to write the next 8 bits.

TXD0 will go high during a transmission if the data is zero.
TXD1 goes high if data is a one. When both pins are low this
is referred to as the Null state.

Typically an ARINC

transmitter chip, such as the HI-8382, HI-8383, HI-8585 or
HI-8586 is connected to these pins to translate the 5 volt
levels to the proper ARINC bus levels.

By writing into the Control Register and reading the Status
Register, the controlling processor can operate the
transmitter independent of the flags at the pins.
Transmission can be initiated by changing CR0 from a 0 to a 1
after the transmitter buffer has been loaded. Then the Status
Register may bemonitored as follows:

SOFTWARE CONTROL OF THE TRANSMITTER

Cabling Noise

Receiver Seems Dead

-The HI-6010 has TTL compatible inputs and

therefore they are susceptible to noise near ground. If the data
bus is passed by ribbon cable or the equivalent to the device
under test, it is possible to get significant glitches on the Master
Reset line. The problem will appear to be a pattern sensitive
failure. One cure is simply to adequately bypass Master Reset.
Another is to buffer the HI-6010 inputs near the chip.

- After Master Reset the HI-6010

receivermustseeawordgapbeforethefirstARINCdatabit.

Error flags must be cleared by either a Status Register Read or
by a Master Reset. The operation of either the transmitter or the
receiver is inhibited upon error.

CONTROL

PROGRAM

PIN 5

BIT NAME

VALUE

OPERATION

CR0

Transmitter is disabled

Transmitter is enabled

CR4

Not in self test

Self test enabled

CR5

8 bit mode + data in 32nd bit

8 bit mode + parity enabled

32 bit mode with parity enabled

8 bit mode with parity enabled

SR0

Do not load the transmitter buffer

Ready to load the transmitter buffer

SR2

Transmission in progress

Transmitter is idle

SR7

No transmission error

8 bit mode only error for underwriting data

STATUS BIT

VALUE

MEANING

HI-6010

HOLT INTEGRATED CIRCUITS

4-6

28 27 26 25

9 13

COMMENTS

Load Control Word D0 = 1

Load Data to Transmit - Byte 1

Status Bits 0, 2 & 7 (

Status Bit 0 Goes High

P T

Load the Next Byte to Transmit

Monitor Status Bit 0

Detect a Transition

P T

Load 3rd Byte

Monitor Status Bit 0

Detect a Transition

P T

Load 4th Byte

TD7

TD6

TD5

TD4

TD3

TD2

TD1

TXRDY, TXE & ERROR)

D16 TD15 TD14 TD13 TD12 TD11 TD10

TD9

D24 TD23 TD22 TD21 TD20 TD19 TD18 TD17

D32 TD31 TD30 TD29 TD28 TD27 TD26 TD25

8 BIT "ONE BYTE AT A TIME" TRANSMIT MONITORING STATUS REGISTER BIT 0

8 BIT "ONE BYTE AT A TIME" TRANSMIT USING TXRDY, PIN 9, TO TRIGGER NEXT BYTE LOAD

28 27 26 25

9 13

COMMENTS

Load Control Word

TXRDY & TXE Go Low After Load Data

Monitor Pin 9 to Go High

P T

After Pin 9 High Then Load Next Byte

Monitor Pin 9 to Go High

P T

Load

Monitor Pin 9 to Go High

P T

Load

Transmission Complete

TD7

TD6

TD5

TD4

TD3

TD2

TD1

D16 TD15 TD14 TD13 TD12 TD11 TD10

TD9

D24 TD23 TD22 TD21 TD20 TD19 TD18 TD17

D32 TD31 TD30 TD29 TD28 TD27 TD26 TD25

HI-6010

RE C/D CS WE D7

HOLT INTEGRATED CIRCUITS

4-7

Электронный компонент: HI-6010CT