HI-8010/HI-8110 Series

The HI-8010 & HI-8110 high voltage display drivers
are constructed of MOS P Channel and N Channel
enhancement mode devices in a single monolithic
structure. They are designed to drive high voltage
liquid crystal displays by converting low level input
signals (TTL on the HI-8010 and CMOS on the
HI-8110) to high voltage drive signals.

Both devices can drive up to 38 segments and
require minimal display-to-data source interfacing.
Serial data is loaded and held in internal latches until
new display data is received.

The HI-8010 & HI-8110 are available in a variety of
ceramic and plastic packaging including leaded and
leadless chip carriers; and J-lead and gull-wing quad
flat packs.

!
!
!

Dichroic Liquid Crystal Displays

Standard Liquid Crystal Displays

Vacuum Fluorescent Displays

! MEMS Drivers

APPLICATIONS

!
!

5 volt input translated to 30 volts or less

Pin-out adaptable to drive 30, 32 or 38

LCD segments

RC oscillator or high voltage (BP) clock input

TTL compatible inputs (HI-8010 only)

CMOS compatible inputs (HI-8110 only)

Low power consumption

Industrial (-40°C to +85°C) & Military (-55°C
to +125°C) temperature ranges

Pin for pin compatible with the Micrel

MIC8010/8011 series and the AMI S4520
series drivers

Cascadable

Military level processing available

PIN CONFIGURATION

(Top View)

FUNCTIONAL BLOCK DIAGRAM

O s c i l l a t o r

D i v i d e r

Vo l t a g e

Tr a n s l a t o r

H i g h Vo l t a g e

B u f f e r

3 8 St a g e

S h i f t R e g i s t e r

3 8 B i t L a t c h

Vo l t a g e

Tr a n s l a t o r s

H i g h Vo l t a g e

D r i v e r s

SEGMENTS

DATA IN

CLK

DOUT 38
DOUT 32
DOUT 30

GENERAL DESCRIPTION

DIN

LCDØ

LCDØ OPT

(See page 5 for additional package pin configurations)

FEATURES

CMOS HIGH VOLTAGE DISPLAY DRIVER

February 2003

S26
S25
S24
S23
S22
S21
S20
DOUT 38
N/C
N/C
N/C
BP
S19

DIN

LCDØ

LCDØOPT

S37
S38

S1
S2
S3
S4
S5
S6

S10

S12

S13

S14

S15

S16

S17

S18

14 15 16 17 18 19 20 21 22 23 24 25 26

51 50 49 48 47 46 45 44 43 42 41 40

S36

S35

S34

S33

S32

S31

S30

S29

S28

S27

HI-8010PQI

HI-8110PQI

HI-8010PQT

HI-8110PQT

52 - PIN

PLASTIC

HOLT INTEGRATED CIRCUITS

www.holtic.com

(DS8010, Rev. D)

02/03

FUNCTIONAL DESCRIPTION

Whenever a Logic "0" is applied to the Chip Select (

)

input, one bit of data is clocked into the shift register from the
serial data input (DIN) with each negative transition of the
Clock (

) input.

is internally tied to VSS on some

versions. A Logic "1" present at the Load (LD) input will
cause a parallel transfer of data from the shift register to the
data latch. If the Load (LD) input is held high while data is
clocked into the shift register, the latch will be transparent.

To display segments, a Logic "1" is stored in the appropriate
shift register bit position, and the segment output is out-of-
phase with the backplane.

The backplane output functions in 1 of 2 modes; externally
driven or self-oscillating. When the LCDØ input is externally
driven with the LCDØOPT input open circuit (Figure 2), the
backplane output will be in-phase with LCDØ. Utilizing the
self-oscillating mode, inputs LCDØ and LCDØOPT are tied
together and connected to an RC circuit (Figure 3).
A 150K

resistor with a 470pF capacitor generates an

approximate backplane frequency of 100Hz. The
LCDØ/LCDØOPT oscillator frequency is divided by 256 to
determine the backplane output frequency.

The resistor

value (R) must be at least 30K

for proper self-oscillator

operation.

For displays having a number of segments greater than 38,
two or more of the display drivers may be cascaded together
by connecting the serial data output (DOUT) from the first
driver, to the serial data input (DIN) of the following driver,
etc. (See Figures 2 & 3). Data out (DOUT) will change state

All four logic inputs are TTL compatible on the HI-8010 and
CMOS compatible on the HI-8110.

HI-8010/HI-8110 Series

INTERNAL OSCILLATOR CIRCUIT

TO BACKPLANE

TRANSLATOR

AND DRIVER

÷ 256

LCDØ

OPT

LCDØ

Figure 1

on the rising edge of the Clock (

). Clock (

), Load (LD)

and Chip Select (

) should be tied in common with each

other, respectively, between all cascaded display drivers.

HOLT INTEGRATED CIRCUITS

SYMBOL

FUNCTION

DESCRIPTION

VSS

POWER

0 Volts

INPUT

Logic input

Chip select

INPUT

Logic input

Clocks shift register on negative edge and DOUT pins on positive edge

INPUT

Logic input

Segment outputs equal shift register data if Load is high

DIN

INPUT

Logic input

Shift register data input

LCD0

INPUT

Analog input

Display clock input and is always bonded out. Can swing from VEE to VDD

LCD0OPT

OUTPUT

Analog output

Bonded out only if an RC oscillator is required

VDD

POWER

5 Volts

VEE

POWER

0 Volts to -30 Volts

DOUT

OUTPUT

Logic output

Selected pinout can provide shift register taps at positions 30, 32, 34, or 38

OUTPUT

Display drive output

Low resistance drive for the backplane and swings from VDD to VEE

Segments

OUTPUT

Display drive output

High resistance drive for each segment and swings from VDD to VEE

PIN DESCRIPTIONS

HI-8010/HI-8110 Series

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Operating Voltage

VDD

3.0

7.0

Supply Current

IDD

Static, No Load

200

µA

IEE

Static, No Load f

=100Hz

150

µA

Input Low Voltage, HI-8010 (except LCDØ)

VIL

0.8

Input High Voltage, HI-8010 (except LCDØ)

VIH

VDD

Input Low Voltage, HI-8110 (except LCD )

VIL

0.3 VDD

Input High Voltage, HI-8110 (except LCD

Input Low Voltage (LCDØ)

VILX

VEE

Input High Voltage (LCDØ)

VIHX

3.5

VDD

Input Current

IIN

VIN = 0 to 5V

µA

Input Capacitance (not tested)

Segment Output Impedance

RSEG

IL = 10µA

Backplane Output Impedance

RBP

IL = 10µA @ 25°C

450

600

Data Out Current:

IDOH

Source Current, VOH = 4.5V

-0.6

IDOL

Sink Current, VOL = 0.5V

0.6

TTL

CMOS

Ø)

VIH

0.7 VDD

VDD

CMOS

DC ELECTRICAL CHARACTERISTICS

VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).

ABSOLUTE MAXIMUM RATINGS

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Voltages referenced to VSS = 0V

VDD........................

VEE................

Supply Voltage

VDD-35V to 0V

0V to 7V

Voltage at any input, except LCD ..-0.3 to VDD+0.3V

Voltage at

input...............VDD-35 to VDD+0.3V

LCDØ

DC Current any input pin...................................10 mA

Power Dissipation......................................................300 mW

Operating Temperature Range - Hi-Temp/Mil..-55° to +125°C

Storage Temperature Range...........................-65° to +150°C

Operating Temperature Range - Industrial........-40° to +85°C

HOLT INTEGRATED CIRCUITS

CASCADING - EXT. OSCILLATOR

DIN

HI-8010J-85

LCDØ

DOUT

SEGMENTS

1 - 32

DIN

HI-8010J-85

LCDØ

DOUT

SEGMENTS

33 - 64

DIN

HI-8010J-85

LCDØ

DOUT

SEGMENTS

65 - 96

BACK

PLANE

LD
CL

Figure 2

CASCADING - RC OSCILLATOR

DIN

HI-8110PQI

LCDØ

DOUT

SEGMENTS

1 - 38

LCDØ OPT

DIN

HI-8110PQI

LCDØ

DOUT

SEGMENTS

39 - 76

LCDØ OPT

DIN

HI-8110PQI

LCDØ

DOUT

SEGMENTS

77 - 114

LCDØ OPT

BACK

PLANE

470pf

150K

LD
CL

Figure 3

HI-8010/HI-8110 Series

HOLT INTEGRATED CIRCUITS

PARAMETER

SYMBOL

VDD

MIN

TYP

MAX

UNITS

Clock Period

1200

Clock Pulse Width

520

Data In - Setup

Data In - Hold

400

Chip Select - Setup to Clock

200

Chip Select - Hold to Clock

450

Load - Setup to Clock

500

Chip Select - Setup to Load

300

Load Pulse Width

500

Chip Select - Hold to Load

300

CSS

CSH

CSL

LCS

Data Out Valid, from Clock

800

CDO

AC ELECTRICAL CHARACTERISTICS

VDD = 5V, VEE = -25V, VSS = 0V, TA = Operating Temperature Range (unless otherwise specified).

TIMING DIAGRAM

CSH

CSS

CDO

CSL

LCS

INPUT

DIN

INPUT

DOUT

OUTPUT

VALID

HI-8010/HI-8110 Series

HOLT INTEGRATED CIRCUITS

ADDITIONAL HI-8010/HI-8110 PIN CONFIGURATIONS

(See page 1 for the 52-Pin Plastic QFP)

S17
S16
S15

S14
S13
S12
S11
S10
S9
S8

S27
S28
S29
S30
S31
S32

N/C

S26

S25

S24

S23

S22

S21

S20

DOUT

S19

S18

DIN

LCDØ

LCDØOPT

18 19 20 21 22 23 24 25 26 27 28

1 44 43 42 41 40

HI-8010J-85

HI-8110J-85

44 - PIN

PLASTIC

PLCC

HI-8010SM-36

HI-8110SM-36

40 - PIN

CERAMIC

LCC

40 39

38 37 36

S25

S24

S23

S22

S21

S20

DOUT 30

S19

S18

16 17 18 19 20 21 22

23 24 25

LCDØOPT

LCDØ

DIN

S30

S29

S28

S27

S26

S10

S12

S13

S14

S15

S16

S17

HI-8010SM-32

HI-8110SM-32

48 - PIN

CERAMIC

LCC

1 48 47 46 45 44 43

19 20 21 22 23 24 25 26 27 28 29 30

S28
S27
S26
S25
S24
S23
S22
S21
S20
DOUT 38
BP
S19

LCDØ

LCDØOPT

V
S37
S38

S1
S2
S3
S4
S5
S6
S7

DIN

S36

S35

S34

S33

S32

S31

S30

S29

S10

S12

S13

S14

S15

S16

S17

S18

HI-8010/HI-8110 Series

HOLT INTEGRATED CIRCUITS

ORDERING INFORMATION

PART

NUMBER OF MASTER PACKAGE

TEMPERATURE

BURN LEAD

NUMBER

SEGMENTS

/SLAVE

DESCRIPTION

RANGE

FLOW

FINISH

TTL Logic Inputs

HI-8010J-85

BOTH

44 PIN PLASTIC J LEAD

-40°C TO +85°C

SOLDER

HI-8010PQI

BOTH

52 PIN PLASTIC QUAD FLAT PACK (PQFP)

-40°C TO +85°C

SOLDER

HI-8010PQT

BOTH

52 PIN PLASTIC QUAD FLAT PACK (PQFP)

-55°C TO +125°C

SOLDER

HI-8010SM-32

BOTH

48 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C

YES SOLDER

HI-8010SM-36

BOTH

40 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C

YES SOLDER

CMOS Logic Inputs

HI-8110J-85

BOTH

44 PIN PLASTIC J LEAD

-40°C TO +85°C

SOLDER

HI-8110PQI

BOTH

52 PIN PLASTIC QUAD FLAT PACK (PQFP)

-40°C TO +85°C

SOLDER

HI-8110PQT

BOTH

52 PIN PLASTIC QUAD FLAT PACK (PQFP)

-55°C TO +125°C

SOLDER

HI-8110SM-32

BOTH

48 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C

YES SOLDER

HI-8110SM-36

BOTH

40 PIN CERAMIC LEADLESS CHIP CARRIER -55°C TO +125°C

YES SOLDER

SEMI-CUSTOM PACKAGING

The above part numbers represent the standard configurations of the HI-8010 & HI-8110 products. They can also be provided with a
varied number of output segments (30, 32 and 38), with either industrial or military screening and in a wide variety of packages. Listed
below are currently available packages. Please contact the Holt Sales Department for your specific requirements.

PACKAGE

DESCRIPTION

LEADS

PLASTIC DUAL-IN-LINE (PDIP)

PLASTIC QUAD FLAT PACK (PQFP)

PLASTIC J-LEAD CHIP CARRIER (PLCC)

CERAMIC DUAL-IN-LINE (CDIP)

CERAMIC LEADLESS CHIP CARRIER (LCC)

CERAMIC J-LEAD CHIP CARRIER

CERAMIC LEADED CHIP CARRIER

Package Type:

PIN NO. 1 IDENT

.045 x 45°

.050 ±.005

(1.27 ±.127)

.045 x 45°

PIN NO. 1

44-PIN PLASTIC PLCC

SEE DETAIL

.172 ±.008

(4.369 ±.203)

DETAIL A

.020 MIN

(.508 MIN)
.025

.045

.690 ±.005

(17.526 ±.127)

SQ.

.610 ±.020

(15.494±.508)

.031±.005

(.787 ±.127)

.653 ±.004

(16.586 ±.102)

SQ.

.017 ±.004

(.432 ±.102)

.015 ± .002

(.381 ±.051)

.009

.011

44J

HI-8010/HI-8110 PACKAGE DIMENSIONS

inches (millimeters)

Package Type: 52PQS

52-PIN PLASTIC QUAD FLAT PACK

HOLT INTEGRATED CIRCUITS

.008

(0.20)

Min.

±.032

.088

.175)

(1.6 ±

Typ.

.394

SQ.

.10)

.004

0° £ Q £ 7°

.009 ±.003R

(.225 ±.075R)

ETAIL

.009 R typ

(0.23 R typ)

.079

(2.00 .05)

±.002

See Detail A

(10.00 ±

.092 ±.004

(2.32 ±.12)

(.88 ±.15)

.012 ±.003

(.30 ±.08)

.035 ±.006

.0256 BSC

(0.65 BSC)

.520 ±.010

(13.2 ±.25)

SQ.

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