HI-8040

GENERAL DESCRIPTION

The HI-8040 is a CMOS integrated circuit designed for high
voltage LCD display drive applications.

It can drive 85

segments at voltages between +5 and -30 volts. An optional
negative converter can generate the negative display drive
voltage. Test inputs facilitate opens and shorts testing. The
backplane frequency is checked and, as long as power is
available, the segments are shut "Off" if the frequency
becomes too low.

The HI-8040 is part of a family of display drivers which
control segment information in the same way.

Data is

serially clocked into the device and the data for all segment
outputs are latched in parallel when the Load input
transitions from high to low. With the Data Out from the shift
register available, devices may be cascaded to obtain more
segment outputs. The shift register is 85 bits long.

The die is metal mask programmable to provide for various
package and/or cascade tap options.

Consult your Holt

Sales representative to explore the possibilities.

!
!

Dichroic Liquid Crystal Displays

Standard Liquid Crystal Displays

APPLICATIONS

4 MHz serial input data rate

85 segment outputs

Cascadable

5 Volt inputs translated to 35 Volts

est pins allow hardware all "ON", all "OFF" or

alternating

Monitors backplane oscillation and forces all
segments to "OFF" condition if below 10Hz

Negative voltage converter available on-chip

CMOS low power

Military processing available

FEATURES

PIN CONFIGURATION

(Top View)

FUNCTIONAL BLOCK DIAGRAM

O s c i l l a t o r

D i v i d e r

V o l t a g e

T r a n s l a t o r

H i g h V o l t a g e

B u f f e r

8 5 S t a g e

S h i f t R e g i s t e r

8 5 B i t L a t c h

V o l t a g e

T r a n s l a t o r s

H i g h V o l t a g e

D r i v e r s

85 SEGMENTS

DIN

BPOSC

BPIN

Þ
Þ

DATA IN

CLK

DOUT

S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12
S11
S10

S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

100 PIN QUAD CERPACK

See page 3-19 for magnified view

HOLT INTEGRATED CIRCUITS

3-15

(DS8040 Rev. NEW)

9/99

September 1999

HI-8040

FUNCTIONAL DESCRIPTION

INPUT LOGIC

BPOSC and BPIN

VEE & NEGATIVE VOLTAGE CONVERTER

must be held low to enter data into the shift register.

The data is clocked on the negative edge of

. LD is nor-

mally held low and only pulsed high when new data is ready
for display. When LD is high the latch is transparent. All four
logic inputs are TTL compatible. A logic "1" at DIN that is
eventually latched to the segment drivers will cause the seg-
ment to be at the opposite voltage level of the BP pin (out of
phase).

The user can either make an oscillator to create the
backplane frequency or drive a signal into BPIN leaving
BPOSC open.

To make an oscillator, pins BPOSC and

BPIN must be connected together and the appropriate R
and C combination applied (See Figure 1). If the oscillator is
used, the backplane frequency is approximately

f =

(for R = 180K

C = 220pF, f

100Hz).

VEE may be externally driven to a maximum -30V. Alterna-
tively, there is a voltage converter that will provide -21.4 volts
(See Figure 2). If the converter pins are left open circuit, an
on-chip sense resistor will cause shut down of all current
consumption associated with the converter. The converter
will survive a shorted segment condition and continue to
maintain VEE at -20 volts.

W &

DOUT

AUTOMATIC SEGMENTS OFF

TEST INPUTS

The DOUT pin is available from segment 85 for cascading
devices to drive more segments and for verifying the data
integrity. This output can drive 2 TTL loads. It changes on the
positive edge of

The internal backplane signal is tested continuously to be at
least 10Hz. If the detector senses f<10Hz, then the segments
are forced to the same voltage as the backplane (all segments
in "OFF" state). However, the detector is only functional while
VDD is above the minimum operating voltage specification.

The test functions available are:

Normal

All Off

All On

Alternating On/Off Segments

The test inputs must be tied to the appropriate logic level for
correct circuit operation.

Display

Control

OSC

R 330K

IN5818, IN5819

330µh

10µF

SENSE

256 RC

HOLT INTEGRATED CIRCUITS

3-16

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

VDD = 5V ±5%, VEE = -21.5V, VSS = 0V, TA = operating temperature range (unless otherwise specified).

PARAMETER

SYMBOL

CONDITION

MIN

TYP

MAX

UNITS

Operating Voltage

VDD

3.0

7.0

Supply Current:

(Converter Off, fBP = 100Hz)

IDD

Static, No Load

300

µA

IEE

Static, No Load

120

µA

Input Low Voltage

(excluding BPIN)

VIL

0.8

Input High Voltage

(excluding BPIN)

VIH

VDD

Input Low Voltage

(BPIN)

VILX

VEE

0.6 VDD

Input High Voltage

(BPIN)

VIHX

0.8 VDD

VDD

Input Current

IIN

VIN = 0 to 5V

100

Input Capacitance

(Guaranteed, not tested)

Segment Output Impedance

RSEG

IL = 10µA

15,000

Backplane Output Impedance

RBP

IL = 10µA

600

Data Out Current:

Source Current

IDOH

VOH = 4.5

-3.0

Sink Current

IDOL

VOL = 0.4

3.2

Voltage Converter:

@ No Load

VEE

See Fig. 2

-22

-21.5

-21

(VDD - VSS = 5V, TA = 25°C)

@ 0.1mA Load

IDD

See Fig. 2

1.8

@ 10K

Load

VEE

See Fig. 2

-20

Offset Voltage

(Guaranteed, not tested)

VOS

See Fig. 4

Voltages referenced to VSS = 0V

PARAMETER

SYMBOL

VDD

MIN

TYP

MAX

UNITS

Clock Period

non-cascaded

tCL

250

cascaded

tCL

500

Clock Pulse Width

non-cascaded

tCW

125

cascaded

tCW

250

Data In - Setup

tDS

Data In - Hold

tDH

Chip Select - Setup to Clock

tCSS

100

Chip Select - Hold to Clock

tCSH

120

Load - Setup to Clock

tLS

120

Chip Select - Setup to Load

tCSL

Load Pulse Width

tLW

130

Chip Select - Hold to Load

tLCS

120

Data Out Valid, from Clock

tCDO

170

VDD = 5V , VEE = -21.5V, VSS = 0V, TA = operating temperature range (unless otherwise specified).

VDD........................

VEE................

Supply Voltage

VDD-35V to 0V

0V to 7V

Voltage at any input, except BPIN....-0.3 to VDD+0.3V

Voltage at BPIN input.................VDD-35 to VDD+0.3V
DC Current any input pin...................................10 mA

Power Dissipation......................................................300 mW

Operating Temperature Range - Hi-Temp/Mil...-55° to +125°C

Storage Temperature Range............................-65° to +150°C

HOLT INTEGRATED CIRCUITS

3-18

Operating Temperature Range - Industrial...... -40° to +85°C

HI-8040

S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13
S12

S11

S10

S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99

100

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

100 PIN QUAD CERPACK

MAGNIFIED VIEW OF PIN ASSIGNMENTS

NUMBER

DESCRIPTION

RANGE

FLOW

FINISH

PART

PACKAGE

TEMPERATURE

BURN

LEAD

HI-8040Q

-40°C to +85°C

SOLDER

100-PIN CERAMIC QUAD FLAT PACK (CQFP)

HI-8040QT

100-PIN CERAMIC QUAD FLAT PACK (CQFP)

-55°C to +125°C

SOLDER

HI-8040QM-01

100-PIN CERAMIC QUAD FLAT PACK (CQFP)

-55°C to +125°C

YES

SOLDER

ORDERING INFORMATION

HOLT INTEGRATED CIRCUITS

3-19

Pin 1

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HI-8040

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: HI-8040