ARINC INPUTS
TEST INPUTS
OUTPUTS
V (A) - V (B)
TEST A
TEST B
OUT A
OUT B
Null
0
0
0
0
Zero
0
0
0
1
One
0
0
1
0
Don't Care
0
1
0
1
Don't Care
1
0
1
0
Don't Care
1
1
0
0
GENERAL DESCRIPTION
The HI-8482 bus interface unit is a silicon gate CMOS de-
vice designed as a dual differential line receiver in accor-
dance with the requirements of the ARINC 429 bus spec-
ification. The device translates incoming ARINC 429 sig-
nals to normal CMOS/TTL levels on each of its two inde-
pendent receive channels. The HI-8482 is also function-
ally equivalent to the Fairchild/Raytheon RM3183.
The self-test inputs force the outputs to either a ZERO,
ONE, or NULL state for system tests. While in self-test
mode, the ARINC inputs are ignored.
All the ARINC inputs have built-in hysteresis to reject
noise that may be present on the ARINC bus. Additional
input noise filtering can also be accomplished with exter-
nal capacitors.
The HI-8482 line receiver is one of several options of-
fered by Holt Integrated Circuits to interface to the ARINC
bus. The digital data processing for serial-to-parallel con-
version and clock recovery can be accomplished with the
HI-6010, HI-8683 or similar devices.
The HI-8482 is available in a variety of ceramic & plastic
packages including Small Outline (SOIC),
DIP & Leadless Chip Carrier (LCC).
J-Lead PLCC,
Cerquad,
FEATURES
!
!
!
!
!
!
Converts ARINC 429 levels to digital data
Direct replacement for the RM3183
Greater than 2 volt receiving hysteresis
TTL and CMOS outputs and test inputs
Military screening available
20-Pin SOIC, PLCC, CERQUAD. DIP &
LCC packages are available
PIN CONFIGURATIONS
(Top Views)
TRUTH TABLE
HI-8482J
HI-8482JT
20 - PIN
PLASTIC
J-LEAD PLCC
18 - IN1A
17 - CAP1B
16 - IN1B
15 - OUT1A
14 - GND
IN2B - 4
OUT2B - 5
IN2A - 6
CAP2A - 7
OUT2A - 8
February 2001
HI-8482PSI
HI-8482PST
20 - PIN
PLASTIC
SMALL
OUTLINE
(SOIC) - WB
20 - TESTB
19 - CAP1A
18 - IN1A
17 - CAP1B
16 - IN1B
15 - OUT1A
14 - GND
13 - N/C
12 - OUT1B
11 - +V
S
-V - 1
TESTA - 2
CAP2B - 3
IN2B - 4
OUT2B - 5
IN2A - 6
CAP2A - 7
OUT2A - 8
+V - 9
N/C - 10
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HOLT INTEGRATED CIRCUITS
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(DS8482 Rev. C)
02/01
DIFF
AMP
TESTA
TESTB
INA
CAPA
INB
CAPB
Comp
LEVEL
SHIFT
LEVEL
SHIFT
Comparators
w / hysteresis
Comp
Detect
Level
Detect
Level
FUNCTIONAL DESCRIPTION
The HI-8482 contains two independent ARINC 429 receive
channels. The diagram in Figure 1 illustrates a typical HI-
8482 receive channel.
The differential ARINC signal input is converted to a positive
signal referenced to ground through level shifters and a
unity gain differential amplifier.
A positive differential input signal is converted to a positive
signal on the plus output of the differential amplifier. This
output is proportional in amplitude to the original input
signal. At the same time, the corresponding MINUS output
is pulled to GND. Likewise when a negative input signal is
present at the ARINC inputs, a positive signal is present on
the MINUS output and the PLUS output is pulled to GND.
The outputs of the differential amplifier are compared with
the ONE, ZERO and NULL threshold levels to produce the
appropriate logic level on the OUTA and OUTB outputs of
the device.
The ARINC clock signal may be recovered
through a NOR function of OUTA and OUTB.
The test inputs logically disconnect the outputs of the
comparators from OUTA and OUTB and force the device
outputs to one of the three valid states (Figure 5). This
alleviates having to ground the ARINC inputs during test
mode operation.
ARINC LEVELS
The ARINC 429 specification requires the following
detection levels:
ONE
+6.5V to +13V
NULL
+2.5V to -2.5V
ZERO
-6.5V to -13V
The HI-8482 guarantees recognition of these levels with a
common mode voltage with respect to GND less than
5V for the worst case condition.
STATE
DIFFERENTIAL VOLTAGE
NOISE
The input hysteresis is set to reject voltage level transitions
in the undefined region between the maximum ZERO level
and the minimum NULL level and the undefined region
between the maximum NULL level and the minimum ONE
level.
Therefore, once a valid input differential voltage
threshold is detected, the outputs will remain at a valid logic
state until a new valid input voltage is detected.
In addition to the hysteresis, the CapA and CapB pinsmake
it possible to add simple RC filters to the ARINC inputs.
HI-8482
HOLT INTEGRATED CIRCUITS
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TYPICAL APPLICATIONS
APPLICATIONS
The standard connections for the HI-8482 are shown in Figure 2.
Decoupling of the supply should be done near the IC to avoid
propagation of noise spikes due to switching transients.
The
ground (GND) connection should be sturdy and isolated from large
switching currents to provide a quiet ground reference.
The HI-8482 can be used with HI-8382 or HI-8585 Line Drivers to
provide a complete analog ARINC 429 interface solution. A simple
application, which can be used in systems requiring a repeater
type circuit for long transmissions or for test interfaces, is given in
Figure 3. More HI-8382 or HI-8585 drivers may be added to test
multiple ARINC channels, as shown.
ARINC RECEIVER STANDARD CONNECTIONS
+5V
+15V
HI-8482
ARINC
CHANNEL 2
LOGIC
TEST
INPUTS
N/C
N/C
OUT2A
OUT1A
OUT1B
A
B
A
B
39 pF
39 pF
39 pF
39 pF
IN1A
IN1B
CAP1A
CAP1B
IN2A
IN2B
CAP2A
CAP2B
TESTA
TESTB
ARINC
CHANNEL 1
CHANNEL 1
DATA OUT
TO LOGIC
CHANNEL 2
DATA OUT
TO LOGIC
-15V
ARINC REPEATER CIRCUIT
ARINC
OUTPUT
CHANNEL 1
ARINC
OUTPUT
CHANNEL 2
ARINC
INPUT
CHANNEL
DATA (A)
DATA (B)
DATA (A)
DATA (B)
OUT1A
OUT1B
IN1A
IN1B
AOUT
BOUT
AOUT
BOUT
A
B
A
B
OUT2B
HI-8482
HOLT INTEGRATED CIRCUITS
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PIN DESCRIPTION TABLE
HI-8482
CAP1A
INPUT
Filter capacitor input for terminal A of
channel 1
CAP1B
INPUT
Filter capacitor input for terminal B of
channel 1
CAP2A
INPUT
Filter capacitor input for terminal A of
channel 2
CAP2B
INPUT
Filter capacitor input for terminal B of
channel 2
GND
POWER
0 Volts
IN1A
INPUT
ARINC input terminal A of channel 1
IN1B
INPUT
ARINC input terminal B of channel 1
IN2A
INPUT
ARINC input terminal A of channel 2
SYMBOL FUNCTION
DESCRIPTION
SYMBOL FUNCTION
DESCRIPTION
IN2B
INPUT
ARINC input terminal B of channel 2
OUT1A
OUTPUT
TTL output terminal A of channel 1
OUT1B
OUTPUT
TTL output terminal B of channel 1
OUT2A
OUTPUT
TTL output terminal A of channel 2
OUT2B
OUTPUT
TTL output terminal B of channel 2
TESTA
INPUT
Test input terminal A
TESTB
INPUT
Test input terminal B
+V
POWER
+5 Volts 10%
+Vs
POWER
+12 Volts 10% or +15 Volts 10%
-Vs
POWER
-12 Volts 10% or -15 Volts 10%
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90%
TIMING DIAGRAMS
FIGURE 4.
ARINC
DIFFERENTIAL
INPUT
+10V
0V
-10V
OUTA
OUTB
t
PLH
t
PHL
t
PLH
t
r
t
PHL
t
f
10%
50%
50%
FIGURE 5.
TESTA
TESTB
+5V
0V
+5V
0V
t
TLH
t
THL
t
TLH
t
r
t
THL
t
f
90%
10%
50%
50%
OUTA (test)
OUTB (test)
HOLT INTEGRATED CIRCUITS
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PARAMETERS
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNITS
ARINC inputs - IN1A, IN1B, IN2A, IN2B
V(A) - V(B)
VIH
OUTA = 1
6.5
10
13
volts
V(A) - V(B)
VIL
OUTB = 1
-6.5
-10
-13
volts
V(A) - V(B)
VNULL
OUTA = OUTB = 0
-2.5
0
2.5
volts
(|V(A)| - |V(B)|) / 2
VCM
Frequency = 80KHz
5
volts
Input resistance - input A to input B
RI
Supply pins floating
30K
50K
ohms
Input resistance - input A or B to Gnd
RG
Supply pins floating
19K
25K
ohms
Input capacitance - input A to B
CI
Filter caps disconnected - see note 1
5
10
pF
Input capacitance - input A or B to Gnd
CG
Filter caps disconnected - see note 1
5
10
pF
Tes t inputs - TESTA, TESTB
Logic 1 input voltage
VIH
ARINC inputs to Gnd
2.7
volts
Logic 0 input voltage
VIL
ARINC inputs to Gnd
0.8
volts
Logic 1 input current (magnitude)
IIH
VIH = 2.7V
5
15
A
Logic 0 input current
IIL
VIL = 0V
0.5
1
A
Outputs - OUT1A, OUT1B, OUT2A, OUT2B
Voltage - sourcing 100A
VOH
TA = 25C
4
volts
Voltage - sourcing 2.8mA
VOH
Full temperature range
3.5
volts
Voltage - sinking 100A
VOL
TA = 25C
0.08
volts
Voltage - sinking 2.0mA
VOL
Full temperature range
0.8
volts
Rise time
tr
CL = 50pF, TA = 25C
40
70
ns
Fall time
tf
CL = 50pF, TA = 25C
30
70
ns
Propagation delay - low to high (ARINC)
tPLH
CL = 50pF, TA = 25C and filter caps disconnected
600
ns
Propagation delay - high to low (ARINC)
tPHL
CL = 50pF, TA = 25C and filter caps disconnected
600
ns
Propagation delay - low to high (TESTA/B)
tTLH
CL = 50pF, TA = 25C
50
ns
Propagation delay - low to high (TESTA/B)
tTHL
CL = 50pF, TA = 25C
50
ns
Supply current
+VS current
IDD
VS = 15V, TA =25C, TESTA and TESTB = 0V
3.7
7
mA
+VS current
IDD
VS = 12V, TA =25C, TESTA and TESTB = 0V
3
6
mA
-VS current
IEE
VS = 15V, TA =25C, TESTA and TESTB = 0V
8.7
15
mA
-VS current
IEE
VS = 12V, TA =25C, TESTA and TESTB = 0V
7.4
14
mA
+VL current
ICC
VS = 15V, TA =25C, TESTA and TESTB = 0V
9
20
mA
+VL current
ICC
VS = 12V, TA =25C, TESTA and TESTB = 0V
8.6
18
mA
HI-8482
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
Voltage at ARINC Inputs: .......................................................-29V to +29V
Voltage at Any Other Input:.............................................-0.3V to V + 0.3V
Output Short Circuit Protected: .............................................Not Protected
Storage Temperature Range: .........................................-65C to +150C
Soldering Temperature: (Ceramic).................................30 sec. at +300C
(Plastic - leads)........................10 sec. at +280C
(Plastic - body) ................................+220C Max.
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Supply Voltage, +V :......................................................................+20 VDC
-V : .......................................................................-20 VDC
+V :........................................................................+7 VDC
Operating Temperature Range: (Industrial) .........................-40C to +85C
(Hi-Temp) ........................-55C to +125C
(Military) ..........................-55C to +125C
Internal Power Dissipation: ..............................................................900mW
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(Voltages referenced to Gnd = 0V)
Notes:
1. Guaranteed by design.
12
V
15, V = +5V, Operating temperature range (unless otherwise noted)
<
<
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