HI-8590
ARINC 429 LINE DRIVER AND LINE RECEIVER
DESCRIPTION
!
Direct ARINC 429 interface to line driver
and line receiver
Line Driver
zener sets output levels
slope control
Mil-temperature range available
!
!
!
!
!
Both functions in a single 16 pin package
Internal
Digital output
CMOS/TTL logic pins
Line Receiver
Input hystersis at least 2 volts
Test inputs bypass analog inputs
Output tri-state mode
Plastic thermally enhanced surface
mount (ESOIC) package
!
!
!
!
!
!
FEATURES
PIN CONFIGURATION
TXAOUT
N/C
V-
GND
TX0IN
RINA
VCC
SUPPLY VOLTAGES
PIN DESCRIPTION TABLE
The HI-8590 is a CMOS integrated circuit with independ-
ent ARINC 429 line driver and line receiver in a single
16 pin package. Both ARINC 429 functions are imple-
mented in analog/digital CMOS.
The line driver function in the HI-8590 connects directly to
the ARINC bus and translates CMOS/TTL input levels to
ARINC 429 specified amplitudes using built-in zeners.
The slope of the differential output signal is controlled by a
single logic input without the use of any external capaci-
tors. A internal 37.5 ohm resistor is provided in series with
each line driver output.
The line driver function is the
same as Holt's 8 pin stand-alone HI-8585 line driver.
The line receiver interfaces directly to the ARINC 429 bus
and translates incoming ARINC levels to levels compati-
ble with CMOS logic. Internal comparator levels are set
just below the standard 6.5 volt minimum data threshold
and just above the standard 2.5 volt maximum null thresh-
old
The TESTA and TESTB inputs of the line receiver allow
bypassing the analog input circuitry for testing purposes.
Also, if both test inputs are taken high, the receiver's digital
outputs are tri-stated allowing wire-or possibilities. The
line driver function is the same as Holt's 8 pin stand-alone
HI-8588 line receiver.
January 2001
PIN
SYMBOL
FUNCTION
DESCRIPTION
1
V+
POWER
+12 TO + 15 VOLTS
2
TESTB
LOGIC INPUT
CMOS
3
ROUTB
LOGIC OUTPUT
RECEIVER CMOS OUTPUT B
4
ROUTA
LOGIC OUTPUT
RECEIVER CMOS OUTPUT A
5
TXBOUT
ARINC OUTPUT
LINE DRIVER TERMINAL B
6
TXAOUT
ARINC OUTPUT
LINE DRIVER TERMINAL A
7
N/C
NO CONNECT
8
V-
POWER
-12 TO -15 VOLTS
9
GND
POWER
GROUND
10
TX1IN
LOGIC INPUT
CMOS OR TTL
11
TX0IN
LOGIC INPUT
CMOS OR TTL
12
RINA
ARINC INPUT
RECEIVER A INPUT
13
RINB
ARINC INPUT
RECEIVER B INPUT
14
TESTA
LOGIC INPUT
CMOS
15
SLP1.5
LOGIC INPUT
CMOS OR TTL, V+ IS OK
16
VCC
POWER
+5 VOLT SUPPLY
3
4
5
6
7
8
10
9
11
12
13
14
15
16
V+
ROUTB
TESTA
TESTB
SLP1.5
ROUTA
RINB
TXBOUT
TX1IN
Vcc =
+5V 5%
V+ = 12V to 15V
V-
= -12V to -15V
1
2
(DS8590 Rev. B)
01/01
HOLT INTEGRATED CIRCUITS
1
HI-8590
FUNCTIONAL DESCRIPTION
Figure 1 is a block diagram of the line driver. The +5V and
-5V levels are generated internally using on-chip zeners.
Currents for slope control are set by zener voltages across
on-chip resistors.
The TX0IN and TX1IN inputs receive logic signals from a
control transmitter chip such as the HI-6010 or HI-8282.
TXAOUT and TXBOUT hold each side of the ARINC bus at
Ground until one of the inputs becomes a One. If for exam-
ple TX1IN goes high, a charging path is enabled to 5V on an
"A" side internal capacitor while the "B" side is enabled to
-5V. The charging current is selected by the SLP1.5 pin. If
SLP1.5 is high, the capacitor is nominally charged from
10% to 90% in 1.5s. If low, the rise and fall times are 10s.
A unity gain buffer receives the internally generated slopes
and differentially drives the ARINC line. Current is limited
by the series output resistors at each pin. There are no
fuses in series with the ARINC outputs of the HI-8590 as
exists on the HI-8382.
The HI-8590 has 37.5 ohms in series with each ARINC out-
put just like the HI-8585. The HI-8586 has 10 ohms in se-
ries. The HI-8586 is used with the HI-8588 for applications
where more series resistance is added externally, typically
for lightning protection devices.
The line driver inputs TX1IN, TX0IN, & SLP1.5 must be tied
to either a logic high or low if not used.
TXAOUT
CURRENT
CONTROL
-5V
5V
ONE
NULL
ZERO
CONTROL
LOGIC
TXBOUT
CURRENT
CONTROL
-5V
5V
SLP1.5
ESD
PROTECTION
AND
VOLTAGE
TRANSLATION
FIGURE 1 - LINE DRIVER BLOCK DIAGRAM
37.5 OHMS
ONE
NULL
ZERO
CONTROL
LOGIC
"A" SIDE
"B" SIDE
FUNCTION TABLES
RINA
RINB
TESTA TESTB ROUTA ROUTB
-1.25V to 1.25V -1.25V to 1.25V
0
0
0
0
-3.25V to -6.5V
3.25V to 6.5V
0
0
0
1
3.25V to 6.5V
-3.25V to -6.5V
0
0
1
0
X
X
0
1
0
1
X
X
1
0
1
0
X
X
1
1
HI-Z
HI-Z
LINE RECEIVER
TX1IN
TX0IN
SLP1.5
0
0
X
0V
0V
0
1
0
-5V
5V
10s
0
1
1
-5V
5V
1.5s
1
0
0
5V
-5V
10s
1
0
1
5V
-5V
1.5s
1
1
X
0V
0V
N /A
SLOPE
N /A
TXAOUT
TXBOUT
LINE DRIVER
37.5 OHMS
LINE DRIVER
HOLT INTEGRATED CIRCUITS
2
HI-8590
FUNCTIONAL DESCRIPTION (cont.)
RINA
RINB
NULL
ZERO
NULL
ONE
TEST
TESTA
TEST
TEST
TESTB
TESTA
'
TESTB
ROUTB
TESTA
'
TESTB
ROUTA
FIGURE 2 - RECEIVER BLOCK DIAGRAM
TEST
R
S
Q
R
LATCH
S
Q
LATCH
ESD
PROTECTION
AND
TRANSLATION
HARDWIRE
OR
DRIVE FROM LOGIC
HI-6010
HI-8590
FIGURE 3 - APPLICATION DIAGRAM
APPLICATION INFORMATION
RECEIVER
Figure 2 shows the general architecture of the ARINC 429
receiver. The receiver operates off the VCC supply only.
The inputs RINA and RINB each have series resistors, typi-
cally 35K ohms. They connect to level translators whose
resistance to Ground is typically 10K ohms. Therefore, any
series resistance added to the inputs will affect the voltage
translation.
After level translation, the inputs are buffered and become
inputs to a differential amplifier. The amplitude of the dif-
ferential signal is compared to levels derived from a di-
vider between VCC and Ground. The nominal settings cor-
respond to a One/Zero amplitude of 6.0V and a Null ampli-
tude of 3.3V.
The status of the ARINC receiver input is latched. A Null
input resets the latches and a One or Zero input sets the
latches.
The logic at the output is controlled by the test signal
which is generated by the logical OR of the TESTA and
TESTB pins.
The receiver output pins float if both
TESTA and TESTB are a logic One.
Figure 3 shows a possible application of the
HI-8590 interfacing both the ARINC transmit
and receive channels of a HI-6010 which in
turn interfaces to an 8-bit microprocessor bus.
2
14
12
13
1
4
3
16
6
5
15
10
11
8
9
HOLT INTEGRATED CIRCUITS
3
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
Line Driver
Input voltage (TX1IN, TX0IN, SLP1.5)
high
V
2.1
-
V+
volts
low
V
-
-
0.5
volts
Input current (TX1IN, TX0IN, SLP1.5)
source
I
V
= 0V
-
-
0.1
A
sink
I
V
= 5V
-
-
0.1
A
ARINC output voltage (TXAOUT, TXBOUT)
one or zero
V
magnitude at pin & no load
4.50
5.00
5.50
volts
null
V
"
" "
"
"
-0.25
-
0.25
volts
ARINC output impedance (TXAOUT, TXBOUT)
Z
Note1
-
37.5
-
ohm
IH
IL
IH
IN
IL
IN
DOUT
NOUT
OUT
Supply Voltages
Vcc ................................................+5V
V+........................+12V 5% or +15V 10%
V-..........................-12V 5% or -15V 10%
Temperature Range
Industrial Screening ............ -40C to +85C
Hi-Temp Screening ........... -55C to +125C
Junction Temperature, Tj .................
175C
5%
+
All voltages referenced to GND
Supply voltages
V
................................................. +7.0V
V+..................................................... +20V
V- ...................................................... -20V
Voltage on inputs
ARINC pin .......................... +29V to - 29V
TX1IN, TX0IN or SLP1.5 ...-0.3 to V+ +0.3
All other input pins............-0.3 to V
+0.3
DC current per input pin ................. +10mA
Power dissipation at 25C
Plastic SO ........................................ 1.0W
Thermal Resistance -
ja .............. 98C/W
Solder Temperature
Leads ....................... +280C for 10 sec
Package body ............................+220C
Storage Temperature ....... -65C to +150C
CC
CC
NOTE: Stresses above absolute maximum
ratings or outside recommended operating
conditions may cause permanent damage to
the device.
These are stress ratings only.
Operation at the limits is not recommended.
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
Vcc = 5V 5%,
GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
V+ = 12V to 15V, V- = -12V to -15V,
DC ELECTRICAL CHARACTERISTICS
HI-8590
Notes :
1. The output resistance is checked by measuring the momentary short circuit current at each ARINC output pin.
HOLT INTEGRATED CIRCUITS
4
DC ELECTRICAL CHARACTERISTICS (cont.)
Vcc = 5V 5%,
GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
V+ = 12V to 15V, V- = -12V to -15V,
HI-8590
AC ELECTRICAL CHARACTERISTICS
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
Line Driver
-
-
Propagation delay
defined in Figure 4, no load
Output high to low
t
500
-
ns
Output low to high
t
500
-
ns
Transition times
Output high to low & low to high
SLP1.5 = logic 1
1.0
1.5
2.0
s
Output high to low & low to high
SLP1.5 = logic 0
5
10
15
s
Line driver input capacitance
Logic
C
-
-
10
pF
phlx
plhx
IN
t
& t
t
& t
Guaranteed but not tested
fx
rx
fx
rx
Vcc = 5V 5%,
GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
V+ = 12V to 15V, V- = -12V to -15V,
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
Line Receiver
-
Operating Supply Current
ARINC input voltage (RINA, RINB)
one or zero
V
differential voltage
6.5
10.0
13.0
volts
null
V
"
"
-
2.5
volts
common mode
V
with respect to GND
-
-
5.0
volts
Logic input voltage (TESTA, TESTB)
high
V
3.5
-
-
volts
low
V
-
-
1.5
volts
ARINC input resistance
RINA to RINB
R
supplies floating
30
75
-
Kohm
RINA or RINB to GND or V
R
"
"
19
40
-
Kohm
Logic input current (TESTA, TESTB)
source
I
V
= 0V
-
-
0.1
A
sink
I
V
= 5V
-
-
0.1
A
Logic output current (ROUTA, ROUTB)
one
I
V
= 4.6V
-
-1.6
-0.8
mA
zero
I
V
= 0.4V
3.6
5.6
-
mA
V
operating (TESTA & TESTB = 0V)
I
-
5.3
8.5
mA
V+
I
no load
-
6.0
12.0
mA
SLP1.5 = V+
V-
I
-12.0
-6.0
-
mA
DIN
NIN
COM
IH
IL
DIFF
CC
SUP
IH
IN
IL
IN
OH
OH
OL
OL
CC -
CC
DD
EE
RINA, RINB open
V+ = +15V
TX1IN, TX0IN = 0V
HOLT INTEGRATED CIRCUITS
5
AC ELECTRICAL CHARACTERISTICS (cont.)
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX UNITS
Line Receiver
-
-
Propagation delay
defined in Figure 5, C = 50pF
Output high to low
t
600
-
ns
Output low to high
t
600
-
ns
Transition times
Output high to low
-
50
80
ns
Output low to high
-
50
80
ns
Line receiver input capacitance (1)
ARINC differential
C
-
5
10
pF
ARINC single ended to GND
C
-
-
10
pF
Logic
L
AD
AS
phlr
plhr
t
t
C
-
-
10
pF
fr
rr
IN
Vcc = 5V 5%,
GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
V+ = 12V to 15V, V- = -12V to -15V,
HI-8590
Notes:
1. All data taken on devices soldered to single layer copper PCB (3" X 4.5" X .062").
2. At 100% duty cycle, 15V power supplies. For 12V power supplies multiply all tabulated values by 0.8.
3. Low Speed: Data Rate = 12.5 Kbps, Load: R = 400 Ohms, C = 30 nF.
4. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF. Data not presented for C = 30 nF as this
is considered unrealistic for high speed operation.
5. 16 Lead Plastic SOIC (Thermally enhanced with built-in heat sink).
6. Similar results would be obtained with TXAOUT shorted to TXBOUT.
7. For applications requiring survival with continuous short circuit, operation above Tj = 175C is not recommended.
HI-8590 PACKAGE THERMAL CHARACTERISTICS
SUPPLY CURRENT (mA)
2
JUNCTION TEMP, Tj (C)
Ta = 25
o
C
Ta = 85
o
C
Ta=125
o
C
Ta = 25
o
C
Ta = 85
o
C
Ta=125
o
C
Low Speed
3
16.7
16.8
16.9
52
112
150
High Speed
4
27.1
26.3
26.1
68
121
162
SUPPLY CURRENT (mA)
2
JUNCTION TEMP, Tj (C)
Ta = 25
o
C
Ta = 85
o
C
Ta=125
o
C
Ta = 25
o
C
Ta = 85
o
C
Ta=125
o
C
Low Speed
3
51.3
46.4
45.7
117
168
194
High Speed
4
46.0
39.7
39.5
122
171
206
PACKAGE STYLE
1
16 Le a d Plastic SOIC
5
M AXIMUM ARINC LOAD
T X AO U T and TXBOUT Shorted to Ground
6, 7
ARINC 429
DATA RATE
ARINC 429
DATA RATE
PACKAGE STYLE
1
16 Le a d Plastic SOIC
5
1. Guaranteed but not tested
Notes:
HOLT INTEGRATED CIRCUITS
6
ORDERING INFORMATION
PART
PACKAGE
TEMPERATURE
BURN
LEAD
NUMBER
DESCRIPTION
RANGE
FLOW
IN
FINISH
HI-8590PSI
16 PIN PLASTIC ESOIC - WB
-40C TO +85C
I
NO
SOLDER
HI-8590PST
16 PIN PLASTIC ESOIC - WB
-55C TO +125C
T
NO
SOLDER
0V
10V
-10V
5V
0V
5V
0V
t rx
t
10%
90%
t
t
10%
90%
t rx
t
phlx
t
phlx
t
plhx
t
10%
plhx
t
TX0IN
FIGURE 4 - LINE DRIVER TIMING
t fx
t
fx
V
TXAOUT - TXBOUT
DIFF
V
RINA -RINB
DIFF
0V
0V
1
-10V
5V
0V
t rr
t rr
t fr
t
10%
90%
t phlr
t
t plhr
t
5V
0V
t plhr
t
t phlr
t
ROUTA
FIGURE 5 - RECEIVER TIMING
HI-8590
TX1IN
ROUTB
Legend:
WB
- Wide Body
ESOIC - Thermally Enhanced Small Outline Package (SOIC w/built-in heat sink)
HOLT INTEGRATED CIRCUITS
7
HI-8590 PACKAGE DIMENSIONS
inches (millimeters)
HOLT INTEGRATED CIRCUITS
8
Package Type:
16-PIN PLASTIC SMALL OUTLINE (ESOIC) - WB
(Wide Body, Thermally Enhanced) - HI-8590 Only
.406
.008
(10.30
.20)
Detail A
.406
.004
(10.30
.10)
7
Typ
0
to 7
.035
.004
(.90
.10)
.0079
.0039
(.20
.10)
.093
.002
(2.35
.05)
Detail A
16HWE2
.295
.004
(7.50
.10)
.0098
(.25)
.140
.002
(3.55
.05)
.018
.002
(.457
.05)
.050
(1.270)
R .040 Typ
(R 1.02 Typ)
.245
.002
(6.23
.05)
Top View
Heat sink stud
on top of
package
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