Optimized for Ultra Low Power Applications
Fabricated on Honeywell's Radiation Hardened
0.55
m
Leff
RICMOSTM IV SOI Process
Array Sizes from 15K to 600K Available Gates
Supports 3.3V and/or 2.5V Operation
Mixed Voltage CMOS Compatible I/O Buffers
Single or dual Port Custom SRAM Drop-In Capability
FEATURES
RICMOSTM LOW POWER SOI GATE ARRAYS
HLX2000
The HLX2000 gate arrays are low power sea-of-transistor
arrays, fabricated on Honeywell's 0.55
m RICMOSTM IV
Silicon On Insulator (SOI) low voltage process. High den-
sity is achieved with the standard 3-layer metal or optional
4-layer metal process, providing up to 310,000 usable
gates. The high density and performance characteristics of
the RICMOS (Radiation Insensitive CMOS) SOI process
make possible device operation beyond 50 MHz over the
full military temperature range, even after exposure to
ionizing radiation exceeding 1x10
6
rad(SiO
2
). Flip-Flops
have been designed for a Soft Error Rate (SER) of less than
1x10
-9
errors/bit/day in the Adams 90% worst case environ-
ment.
Each HLX2000 design is founded on our proven RICMOS
ASIC library of SSI and MSI logic elements, custom RAM
cells and selectable I/O pads. These low power gate arrays
feature a global clock network capable of handling multiple
clock signals with low clock skew between registers. This
family is fully compatible with Honeywell's high reliability
screening procedures and consistent with QML Class Q
and V requirements.
Designers can choose from a wide variety of I/O types.
Output buffer options include 8 drive strengths, IEEE
1149.1 boundary scan, pull-up/pull-down resistors, and
three-state capability. Input buffers can be selected with
IEEE 1149.1 boundary scan, and pull-up/pull-down resis-
tors. Bi-directional buffers are also available.
Another important feature is the dual voltage I/O capability
in which the designer has complete flexibility in terms of
placement of I/O buffers. This feature allows adjacent I/O
buffers with different supply voltages.
The HLX2000 family provides options for custom drop-in
SRAM macrocells. Word widths can be selected in two bit
increments. Single port and two port options are available.
The HLX2000 family has a special feature to allow a chip
level power down mode, in which the associated buses
connected to the chip can remain active. This high imped-
ance off-state buffer feature allows users to power down
portions of their system for power savings or for cold
sparing.
Logic designers need not have prior experience in radiation
hardening. Honeywell's VDSTM Toolkit and RICMOS IV SOI
libraries provide the necessary guidance to achieve first
pass design success. The VDS Toolkit supports industry
standard platforms including those offered by Mentor
Graphics and Synopsys.
Honeywell can perform design translations to the HLX2000
arrays from other CAD platforms. Our synthesis capabilities
allow customers to use familiar CAD tools and libraries to
map the existing designs to Honeywell library components.
GENERAL DESCRIPTION
Supports System Speeds Beyond 50 MHz
Supports Chip Level Power Down for Cold Sparing
Total Dose Hardness
1x10
6
rad(SiO
2
)
Soft Error Rate
1x10
-9
Errors/Bit-Day*
No Latchup
FAMILY
*Projected
2
HLX2000
Helping You Control Your World
Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability
arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
900170 Rev. C
2/97
To learn more about Honeywell Solid State Electronics Center, visit our web site at
http://www.ssec.honeywell.com
(1) Projected
*Planned Arrays
(2) Design and package dependent
The HLX2000 family of gate arrays is the right choice for
your high reliability applications demanding low power and
high radiation hardness.
To learn more about Honeywell's variety of space compo-
nents, call us at 612-954-2888.
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