GDC21D301A
(Transport Decoder)
Version 1.5
HDS-GDC21D301A-9908 / 10
3
GDC21D301A
The information contained herein is subject to change without notice.
The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by Hyundai for any infringements of patents or other rights of the third parties
which may result from its use. No license is granted by implication or otherwise under any patent or
patent rights of Hyundai or others.
These Hyundai products are intended for usage in general electronic equipment (office equipment,
communication equipment, measuring equipment, domestic electrification, etc.).
Please make sure that you consult with us before you use these Hyundai products in equipment which
require high quality and / or reliability, and in equipment which could have major impact to the welfare of
human life (atomic energy control, airplane, spaceship, traffic signal, combustion control, all types of
safety devices, etc.). Hyundai cannot accept liability to any damage which may occur in case these
Hyundai products were used in the mentioned equipment without prior consultation with Hyundai.
Copyright 1999 Hyundai Micro Electronics Co.,Ltd.
All Rights Reserved
4
GDC21D301A
TABLE OF CONTENTS
1. General Description................................................................................................................. 5
2. Features .................................................................................................................................... 5
3. Pin Description......................................................................................................................... 6
4. Block Diagram ........................................................................................................................ 12
5. Functional Description .......................................................................................................... 13
5.1 Forward-Error-Correction (FEC) Interface........................................................................ 13
5.2 Sync Detector ................................................................................................................... 13
5.3 TS Header Decoder .......................................................................................................... 13
5.4 Adaptation Field Decoder ................................................................................................. 13
5.5 PES Decoder .................................................................................................................... 13
5.6 Memory Controller ............................................................................................................ 14
5.7 High-Speed Interface........................................................................................................ 14
5.8 External Decoder Interface ............................................................................................... 14
5.9 Host Interface ................................................................................................................... 14
5.10 Clock Controller .............................................................................................................. 14
6. Register Description.............................................................................................................. 15
7. Electrical Specification.......................................................................................................... 30
7.1 Absolute Maximum Rating................................................................................................ 30
7.2 Recommended Operating Range ..................................................................................... 30
7.3 DC Characteristics (VDD = 3.3 V
10%, TA = 0 ~ 70
C ) .............................................. 30
7.4 AC Characteristics (VDD = 3.3 V
10%, TA = 0 ~ 70
C ) .............................................. 31
7.4.1 Transport Stream Interface Requirements.................................................................. 31
7.4.2 Clock Interface Requirements..................................................................................... 31
7.4.3 Reset Signal Requirement .......................................................................................... 32
7.4.4 Audio/Video/Data Decoder Interface Requirements ................................................... 32
7.4.5 Host Processor Interface Requirements ..................................................................... 33
8. Package Mechanical Data ..................................................................................................... 34
8.1 Package Pin out................................................................................................................ 34
8.2 Package Dimensions ........................................................................................................ 36
5
GDC21D301A
1. General Description
The GDC21D301A Transport Decoder
resides in the center of an MPEG-2 decoding
system. It accepts MPEG-2 transport streams,
parses the transport and packetized
elementary stream (PES) layers into the
separate data streams, and provides rate
buffering for the parsed data streams. Then it
passes those data streams to video and audio
decoders. The GDC21D301A also extracts
Program Clock Reference (PCR) in the data
stream and provides the Pulse Width
Modulation (PWM) signals in order to
recover the clock and to synchronize the
playback of video and audio. The
GDC21D301A manages an external DRAM
that is used for data storage and buffering the
various parsed data streams. This DRAM is
shared with the host processor so that the
system's memory requirements can be
consolidated into a single, low-cost DRAM.
The GDC21D301A stores data packets
destined for the host directly in shared
DRAM for easy access by the host.
2. Features
The GDC21D301A is fully compliant with MPEG-
2 ISO/IEC 13818-1 specification.
Decoding Features
Performs MPEG-2 transportation and PES layer
handling
Supports maximum 80 Mbps transport streams
Provides a high-speed data output port
Identifies and extracts up to 32 transport stream
(TS) packet PIDs
PCR & Time Stamp Control Features
Provides two PWM signals to recover the system
clock
Provides the instant value of internal STC
counter when a frame begins
Extracts PTS and DTS of video and audio for
Lip-synchronization
Interface
Supports byte-parallel/bit-serial TS input
Supports video/audio PES layer or elementary
stream layer output
Provides error code insertion capability in video
elementary stream
Supports an external error input signal for
declaring an erroneous packet
Supports 8/16-bit host bus interface
GDC21D301A
Transport Decoder
6
GDC21D301A
3. Pin Description
Figure 1. Pin Description
4 5
8 9
1 3 3
1 7 6
1
H M E
G D C 2 1 D 3 0 1 A
Y Y W W
D S P _ D A T A [ 1 3 ]
D S P _ D A T A [ 1 4 ]
D S P _ D A T A [ 1 5 ]
V S S
D S P _ I N T
D S P _ R E A D Y
V D D
T D O 0
T D O 1
V D D
H S D E N
H I G H _ S P _ D A T A [ 1 ]
H I G H _ S P _ D A T A [ 0 ]
C L O C K _ O U T
V S S
T A [ 7 ]
T A [ 6 ]
T A [ 5 ]
T A [ 4 ]
T A [ 3 ]
T A [ 2 ]
T A [ 1 ]
T A [ 0 ]
V S S
T W E B
T E S T
T D I
P _ S _ M O D E
F _ S T A R T
F E C _ D A T A [ 7 ]
F E C _ D A T A [ 6 ]
F E C _ C L O C K
V D D
N C
V S S
F E C _ D A T A [ 5 ]
F E C _ D A T A [ 4 ]
F E C _ D A T A [ 3 ]
F E C _ D A T A [ 2 ]
F E C _ D A T A [ 1 ]
F E C _ D A T A [ 0 ]
E R R _ B L O C K _ B
D _ V A L I D
S C A N _ M O D E /T A [ 8 ]
DRAM_
DATA[2]
VSS
DRAM_
DATA[3]
DRAM_
DATA[4]
DRAM_
DATA[5]
DRAM_
DATA[6]
VDD
DRAM_
DATA[7]
DRAM_
DATA[8]
DRAM_
DATA[9]
DRAM_
DATA[10]
VSS
DRAM_
DATA[11]
DRAM_
DATA[12]
DRAM_
DATA[13]
DRAM_
DATA[14]
VSS
NC
VDD
CLOCK_27M
VDD
DRAM_
DATA[15]
\DRAM_CAS0
\DRAM_CAS1
\DRAM_RAS0
VSS
\DRAM_RAS1
DRAM_RO
W
_COL_
ADDR[0]
DRAM_RO
W
_COL_
ADDR[1]
DRAM_RO
W
_COL_
ADDR[2]
VDD
DRAM_RO
W
_COL_
ADDR[3]
DRAM_RO
W
_COL_
ADDR[4]
DRAM_RO
W
_COL_
ADDR[5]
DRAM_RO
W
_COL_
ADDR[6]
VSS
DRAM_RO
W
_COL_
ADDR[7]
DRAM_RO
W
_COL_
ADDR[8]
DRAM_RO
W
_COL_
ADDR[9]
DRAM_R
W
B
VDD
M16
SCAN_IN1
/
TA[9]
SCAN_TEST
N C
N C
V S S
\ D S P _ P D
D S P _ R W B
\ D S P _ S T R B
V P W M
\ V I D _ S T R B
V D D
\ V I D _ D C S
V A D _ D A T A [ 0 ]
V D D
V A D _ D A T A [ 1 ]
V A D _ D A T A [ 2 ]
V S S
V A D _ D A T A [ 3 ]
V A D _ D A T A [ 4 ]
V A D _ D A T A [ 5 ]
V A D _ D A T A [ 6 ]
V D D
\ R E S E T
S C A N _ O U T 1
V A D _ D A T A [ 7 ]
P T S _ D T S _ S T R B
\ D A T A _ S T R B
\ D A T A _ D C S
V S S
\ A U D _ S T R B
A U D _ S E R _ D A T A
\ A U D _ D C S
V S S
A P W M
V D D
B O F _ V
B O F _ A
B O F _ D
\ V I D _ R E Q
\ V I D _ W A I T
\ A U D _ R E Q
\ A U D _ W A I T
\ D A T A _ R E Q
\ D A T A _ W A I T
D R A M _ D A T A [ 0 ]
D R A M _ D A T A [ 1 ]
DSP_
DATA[12]
VDD
DSP_
DATA[11]
DSP_
DATA[10]
DSP_
DATA[9]
DSP_
DATA[8]
VSS
DSP_
DATA[7]
DSP_
DATA[6]
DSP_
DATA[5]
DSP_
DATA[4]
VDD
DSP_
DATA[3]
DSP_
DATA[2]
DSP_
DATA[1]
DSP_
DATA[0]
VSS
NC
VDD
CLOCK
BIT8MODE
DSP_
ADDR[0]
DSP_
ADDR[1]
DSP_
ADDR[2]
DSP_
ADDR[3]
DSP_
ADDR[4]
DSP_
ADDR[5]
DSP_
ADDR[6]
DSP_
ADDR[7]
DSP_
ADDR[8]
DSP_
ADDR[9]
DSP_
ADDR[10]
DSP_
ADDR[11]
DSP_
ADDR[12]
DSP_
ADDR[13]
DSP_
ADDR[14]
DSP_
ADDR[15]
DSP_
ADDR[16]
DSP_
ADDR[17]
DSP_
ADDR[18]
DSP_
ADDR[19]
DSP_
ADDR[20]
DSP_
ADDR[21]
DSP_
ADDR[22]
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