Document Outline

• CONTENTS
  • 1. OVERVIEW 1
  • 1.1 Description 1
  • 1.2 Features 1
  • 1.3 Development Tools 1
  • 2. BLOCK DIAGRAM 3
  • 3. PIN ASSIGNMENT (Top View) 4
  • 4. PACKAGE DIMENSION 7
  • 4.1 28 SOP PIN DIMENSION (DIMENSIONS IN INCH) 7
  • 4.2 28 Skinny DIP PIN DIMENSION (DIMENSIONS IN INCH) 7
  • 4.3 40 PDIP Pin Dimension (dimension in inch) 8
  • 4.4 44 PLCC Pin Dimension (dimension in mm) 8
  • 4.5 44 QFP Pin Dimension (dimension in mm) 9
  • 5. PIN FUNCTION 10
  • 6. PORT STRUCTURES 12
  • 6.1 R0 Ports 12
  • 6.2 R1 Ports (R10, R11, R12, R13, R14) 12
  • 6.3 R1 Ports (R15, R16, R17) 13
  • 6.4 R2, R3, R4 Ports 13
  • 6.5 REMOUT Port 14
  • 6.6 Xin, Xout Ports 14
  • 6.7 RESET Port 14
  • 6.8 TEST Port 15
  • 7. ELECTRICAL CHARACTERISTICS 16
  • 7.1 Absolute maximum ratings ( Ta=25 �C) 16
  • 7.2 Recommended Operating Ranges 16
  • 7.3 DC characteristics (VDD=2.2~5.5, Vss=0, Ta=0~70 �C) 17
  • 7.4 REMOUT Port Ioh characteristics graph 18
  • 7.5 REMOUT port Iol characteristics graph 18
  • 7.6 AC characteristics (VDD=2.2~5.5V, Vss=0V, Ta=0~70�C) 19
  • 8. MEMORY ORGANIZATION 21
  • 8.1 Registers 21
  • 8.2 Program Memory 24
  • 8.3 Data Memory 27
  • 8.4 Addressing Mode 30
  • 9. I/O PORTS 34
  • 9.1 R0 Ports 34
  • 9.2 R1 Ports 34
  • 9.3 R2 Port 36
  • 10. CLOCK GENERATOR 39
  • 10.1 Operation Mode 41
  • 11. TIMER 42
  • 11.1 Basic Interval Timer 42
  • 11.2 Timer0, Timer1, Timer2 44
  • 12. INTERRUPTS 57
  • 12.1 Interrupt priority and sources. 57
  • 12.2 INTERRUPT CONTROL REGISTER 58
  • 12.3 INTERRUPT ACCEPT MODE 59
  • 12.4 INTERRUPT PROCESSING SEQUENCE 60
  • 12.5 SOFTWARE INTERRUPT (Interrupt by Break (BRK) Instruction) 61
  • 12.6 MULTIPLE INTERRUPT 62
  • 12.7 Key Scan Input Processing 62
  • 13. WATCH DOG TIMER 66
  • 13.1 Control of WDT 66
  • 13.2 WDT Interrupt Interval 67
  • 14. STANDBY FUNCTION 69
  • 14.1 Sleep Mode 69
  • 14.2 STOP MODE 69
  • 14.3 STANDBY MODE RELEASE 71
  • 14.4 RELEASE OPERATION OF STANDBY MODE 72
  • 15. OSCILLATION CIRCUIT 74
  • 16. RESET FUNCTION 75
  • 16.1 EXTERNAL RESET 75
  • 16.2 POWER ON RESET 75
  • 16.3 Low Voltage Detection Mode 76
  • 16.4 Low Voltage Indicator Register (LVIR) 79
• GMS81C5016 GMS81C5024 GMS81C5032
  • CMOS SINGLE CHIP 8-BIT MICROCONTROLLER
  • FOR UR (Universal Remocon) & WIRELESS KEYBOARD
• 1. OVERVIEW
  • 1.1 Description
  • 1.2 Features
  • 1.3 Development Tools
• 2. BLOCK DIAGRAM
• 3. PIN ASSIGNMENT (Top View)
• 4. PACKAGE DIMENSION
  • 4.1 28 SOP PIN DIMENSION (DIMENSIONS IN INCH)
  • 4.2 28 Skinny DIP PIN DIMENSION (DIMENSIONS IN INCH)
  • 4.3 40 PDIP Pin Dimension (dimension in inch)
  • 4.4 44 PLCC Pin Dimension (dimension in mm)
  • 4.5 44 QFP Pin Dimension (dimension in mm)
• 5. PIN FUNCTION
• 6. PORT STRUCTURES
  • 6.1 R0 Ports
  • 6.2 R1 Ports (R10, R11, R12, R13, R14)
  • 6.3 R1 Ports (R15, R16, R17)
  • 6.4 R2, R3, R4 Ports
  • 6.5 REMOUT Port
  • 6.6 Xin, Xout Ports
  • 6.7 RESET Port
  • 6.8 TEST Port
• 7. ELECTRICAL CHARACTERISTICS
  • 7.1 Absolute maximum ratings ( Ta=25 �C)
  • 7.2 Recommended Operating Ranges
  • 7.3 DC characteristics (VDD=2.2~5.5, Vss=0, Ta=0~70 �C)
  • 7.4 REMOUT Port Ioh characteristics graph
  • 7.5 REMOUT port Iol characteristics graph
  • 7.6 AC characteristics (VDD=2.2~5.5V, Vss=0V, Ta=0~70�C)
    • Figure 7-1 Clock, Interrupt, RESET, EC Input Timing
• 8. MEMORY ORGANIZATION
  • 8.1 Registers
    • Figure 8-1 Configuration of Registers
      • Accumulator:
    • Figure 8-2 Configuration of YA 16-bit Register
      • X, Y Registers:
      • Stack Pointer:
    • Figure 8-3 Stack Operation
      • Program Counter:
      • Program Status Word:
      • [Carry flag C]
      • [Zero flag Z]
    • Figure 8-4 PSW (Program Status Word) Register
      • [Interrupt disable flag I]
      • [Half carry flag H]
      • [Break flag B]
      • [Direct page flag G]
      • [Overflow flag V]
      • [Negative flag N]
  • 8.2 Program Memory
    • Figure 8-5 Program Memory Map
    • Figure 8-6 Interrupt Vector Area
    • Figure 8-7 PCALL and TCALL Memory Area
      • PCALL� rel
      • TCALL� n
  • 8.3 Data Memory
    • Figure 8-8 Data Memory Map
      • User Memory
      • Control Registers
      • Stack Area
  • 8.4 Addressing Mode
    • (1) Register Addressing
    • (2) Immediate Addressing � #imm
    • (3) Direct Page Addressing � dp
    • (4) Absolute Addressing � !abs
    • (5) Indexed Addressing
    • X indexed direct page (no offset) � {X}
    • X indexed direct page, auto increment� {X}+
    • X indexed direct page (8 bit offset) � dp+X
    • Y indexed direct page (8 bit offset) � dp+Y
    • Y indexed absolute � !abs+Y
    • Direct page indirect � [dp]
    • X indexed indirect � [dp+X]
    • Y indexed indirect � [dp]+Y
    • Absolute indirect � [!abs]
• 9. I/O PORTS
  • 9.1 R0 Ports
    • (1) R0 I/O Data Direction Register (R0DD)
    • (2) R0 Data Register (R0)
    • (3) R0 Open drain Assign Register (R0ODC)
    • (4) R0 Pull-up Resistor Control Register (R0PC)
  • 9.2 R1 Ports
    • (1) R1 I/O Data Direction Register (R1DD)
    • (2) R1 Data Register (R1)
    • (3) R1 Mode Register (PMR1)
      • Table 9-1 Selection mode of PMR1
    • (4) R1 Pull-up Resistor Control Register (R1PC)
  • 9.3 R2 Port
    • (1) R2 I/O Data Direction Register (R2DD)
    • (2) R2 Data Register (R2)
    • (3) R2 Open drain Assign Register (R2ODC)
    • (4) R2 Pull-up Resistor Control Register (R2PC)
    • R3 Port
    • (1) R3 I/O Data Direction Register (R3DD)
    • (2) R3 Data Register (R3)
    • (3) R3 Open drain Assign Register (R3ODC)
    • (4) R3 Pull-up Resistor Control Register (R3PC)
    • R4 Port
    • (1) R4 I/O Data Direction Register (R4DD)
    • (2) R4 Data Register (R4)
    • (3) R4 Open drain Assign Register (R4ODC)
    • (4) R4 Pull-up Resistor Control Register (R4PC)
• 10. CLOCK GENERATOR
  • Figure 10-1 Block Diagram of Clock Generator
  • Figure 10-2 Block diagram of Prescaler
    • Table 10-1 ps output period
  • Figure 10-3 Clock Control Register
  • 10.1 Operation Mode
    • Main-clock operating mode
    • STOP mode
    • Figure 10-4 Operating Mode
• 11. TIMER
  • 11.1 Basic Interval Timer
    • Figure 11-1 Block Diagram of Basic Interval Timer
      • (1) Control of B.I.T
    • Figure 11-2 BTCL mode of B.I.T
      • (2) Input clock selection of B.I.T
    • Figure 11-3 Basic Interval Timer Interrupt Time
      • (3) Reading Basic Interval Timer
  • 11.2 Timer0, Timer1, Timer2
    • (1) Timer Operation Mode
    • Figure 11-4 Timer / Counter Block diagram
      • (2) Function of Timer & Counter
    • Figure 11-5 Block Diagram of Timer0
    • Figure 11-6 Block Diagram of Timer1
    • Figure 11-7 Block Diagram of Timer2
    • Figure 11-8 Timer0 / Timer1 Mode Register
    • Figure 11-9 Timer0 Mode Register
    • Figure 11-10 Timer1 Mode Register
    • Figure 11-11 Timer2 Mode Register
    • Figure 11-12 External Interrupt Signal Edge Selection Register
      • (3) Timer0, Timer1
    • Figure 11-13 Operatiion of Timer0
    • Figure 11-14 Start/Stop operation of Timer0
    • Figure 11-15 Input capture operation of Timer0
      • * Single/Modulo-N Mode
    • Figure 11-16 Operation Diagram for Single/Modulo-N Mode
      • (4) Timer 2
    • Figure 11-17 Operation of Timer2
    • Figure 11-18 Start/Stop of Timer2
• 12. INTERRUPTS
  • Figure 12-1 Block Diagram of Interrupt
  • 12.1 Interrupt priority and sources.
    • Table 12-1 Interrupt Priority & Source
  • 12.2 INTERRUPT CONTROL REGISTER
  • 12.3 INTERRUPT ACCEPT MODE
    • (1) Selection of Interrupt by IP3-IP0
      • Table 12-2 Interrupt Selection by IP3 - IP0
    • (2) Interrupt Timing
    • Figure 12-2 Interrupt Enable Accept Timing
      • (3) The valid timing after executing Interrupt control instructions
  • 12.4 INTERRUPT PROCESSING SEQUENCE
    • Figure 12-3 Interrupt Procesing Step Timing
  • 12.5 SOFTWARE INTERRUPT (Interrupt by Break (BRK) Instruction)
    • Figure 12-4 Execution of BRK or TCALL0
  • 12.6 MULTIPLE INTERRUPT
  • 12.7 Key Scan Input Processing
    • (1) Standby Mode Release Register (SMRR)
    • Figure 12-5 Key Scan Block
      • (2) Standby Release Level Control Register (SRLC)
• 13. WATCH DOG TIMER
  • Figure 13-1 Block diagram of Watch Dog Timer
  • 13.1 Control of WDT
  • 13.2 WDT Interrupt Interval
• 14. STANDBY FUNCTION
  • 14.1 Sleep Mode
  • 14.2 STOP MODE
    • Figure 14-1 Block Diagram of Standby Circuit
    • Figure 14-2 ENPCK and Basic Interval Timer Clock
  • 14.3 STANDBY MODE RELEASE
    • Table 14-1 Standby Mode Register
    • Table 14-2 Standby Mode Release
    • Figure 14-3 Release Timing of Standby Mode
  • 14.4 RELEASE OPERATION OF STANDBY MODE
    • (1) Interrupt Enable Flag(I) of PSW = ``0``
    • (2) Interrupt Enable Flag(I) of PSW = ``1``
    • Figure 14-4 Standby Mode Release Flow
      • Table 14-3 Operation State in Standby Mode
• 15. OSCILLATION CIRCUIT
  • Figure 15-1 Oscillator configurations
• 16. RESET FUNCTION
  • 16.1 EXTERNAL RESET
    • Figure 16-1
  • 16.2 POWER ON RESET
    • Figure 16-2 Block Diagram of Power On Reset Circuit
    • Figure 16-3 Oscillator stabilization diagram
    • Figure 16-4 Reset Timing by Diagram
  • 16.3 Low Voltage Detection Mode
    • (1) Low voltage detection condition
    • (2) Low Voltage Detection Mode
    • (3) Release of Low Voltage Detection Mode
    • Figure 16-5 Low Voltage vs Temperature
      • (4) SRAM BACK-UP after Low Voltage Detection.
    • Figure 16-6 Low Voltage Detection and Protection
      • (5) S/W flow chart example after Reset using SRAM Back-up
    • Figure 16-7 S/W Flow Chart Example for SRAM Back-up
  • 16.4 Low Voltage Indicator Register (LVIR)
• 1. Instruction Map
• 2. Alphabetic order table of instruction
  • 2.1 Instruction Table by Function
• 1. General Circuit Diagram of GMS81C5016/24/32
• 2. Mask Option List Example Refer to Circuit B-1
• 3. Key Scan
  • * Current Consumption