The GM71V18163CJ-6E is the new
g e n e r a t i o n d y n a m i c R A M o r g a n i z e d
1,048,576 x 16 bit. GM71V18163CJ-6E has
realized higher density, higher performance
and various functions by utilizing advanced
C M O S p r o c e s s t e c h n o l o g y . T h e
GM71V18163CJ-6E offers Extended Data
out(EDO) Mode as a high speed access
mode. Multiplexed address inputs permit the
GM71V18163CJ-6E to be packaged in
standard 400 mil 42pin plastic SOJ. The
package size provides high system bit
densities and is compatible with widely
available automated testing and insertion
equipment.
Description
Features
* 1,048,576 Words x 16 Bit Organization
* Extended Data Out Mode Capability
* Single Power Supply (3.3V+/-0.3V)
* Fast Access Time & Cycle Time
(Unit: ns)
Pin Configuration
1,048,576 WORDS x 16 BIT
EDO DRAM-ET Part
GM71V18163CJ-6E
t
RAC
t
CAC
t
RC
t
HPC
60
15
104
25
* Low Power
Active : 684/612/540mW (MAX)
Standby : 7.2mW (CMOS level : MAX)
0.83mW (L-version : MAX)
* /RAS Only Refresh, /CAS before /RAS Refresh,
Hidden Refresh Capability
* All inputs and outputs TTL Compatible
* 1024 Refresh Cycles/16ms
* 2 CAS byte Control
(Top View)
GM71V18163CJ-6E
V
SS
I/O15
I/O14
I/O13
I/O12
38
39
40
41
42
I/O11
I/O10
I/O9
I/O8
NC
32
33
34
35
36
V
SS
37
/LCAS
/UCAS
/OE
29
30
31
A9
A8
A7
26
27
28
A6
A5
A4
23
24
25
V
SS
22
V
CC
I/O0
I/O1
I/O2
I/O3
1
2
3
4
5
I/O4
I/O5
I/O6
I/O7
NC
7
8
9
10
11
V
CC
6
NC
/WE
/RAS
12
13
14
NC
NC
A0
15
16
17
A1
A2
A3
18
19
20
V
CC 21
42 SOJ
Rev 0.1 / Apr'01
GM71V18163CJ-6E
Pin Description
Pin
Function
Pin
Function
A0-A9
A0-A9
I/O0-I/O15
/RAS
/WE
V
CC
V
SS
NC
Address Inputs
Refresh Address Inputs
Data-In/Out
Row Address Strobe
Read/Write Enable
Power (+3.3V)
Ground
No Connection
Ordering Information
Column Address Strobe
/OE
Output Enable
Absolute Maximum Ratings*
Type No.
Access Time
Package
GM71V18163CJ 6E
60ns
400 Mil
42 Pin
Plastic SOJ
Symbol
Parameter
Rating
Unit
T
A
T
STG
V
IN/OUT
V
CC
I
OUT
-30 ~ 85
-55 ~ 125
-0.5 ~ Vcc+0.5
(<=4.6V(MAX))
-0.5 ~ 4.6
50
Ambient Temperature under Bias
Storage Temperature
Voltage on any Pin Relative to V
SS
Supply Voltage Relative to V
SS
Short Circuit Output Current
V
V
mA
P
D
1.0
Power Dissipation
W
C
C
/UCAS, /LCAS
Note: Operation at or above Absolute Maximum Ratings can adversely affect device reliability.
Rev 0.1 / Apr'01
GM71V18163CJ-6E
Truth Table
/RAS
/LCAS /UCAS
/WE
/OE
H
L
L
L
D
H
L
H
D
H
H
L
D
H
H
H
D
D
L
L
Output
Open
Valid
Valid
Valid
Lower byte
Upper byte
Word
Operation
Standby
/RAS-only
Refresh cycle
Read cycle
L
L
L
L
L
L
H
L
H
Early write cycle
L
H
L
L
H
Open
Open
Open
L
L
L
L
Undefined
Delayed Write
cycle
L
L
L
H
H
H to L
L
CBR Refresh
or
Self Refresh
(L-series)
H to L
H
L
H to L
L
L
Notes
1,3
1,3
1,3
1,3
1,3
1,2,3
1,2,3
1,3
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Undefined
Undefined
Open
Open
Open
Open
Open
Valid
Valid
Valid
Word
Word
Word
Word
Read-modify
-write cycle
Read cycle
(Output disabled)
D
D
H to L
H to L
H to L
L
L
L
L
L
L
L
H
L
L
L
L
H
D
D
L
H
H
H
H
L
D
D
D
D
D
D
L to H
L to H
L to H
L
L
L
L
Recommended DC Operating Conditions
(TA = -30 ~ 85C)
Symbol
Parameter
Unit
V
CC
V
IH
V
IL
Supply Voltage
Input High Voltage
Input Low Voltage
V
V
V
Max
3.6
V
CC
+ 0.3
0.8
Typ
3.3
-
-
Min
3.0
2.0
-0.3
Note: All voltage referred to Vss.
The supply voltage with all VCC pins must be on the same level. The supply voltage
with all VSS pins must be on the same level.
Notes: 1. H: High (inactive) L: Low(active) D: H or L
2.
t
WCS
>= 0ns Early write cycle
t
WCS
<= 0ns Delayed write cycle
3. Mode is determined by the OR function of the /UCAS and /LCAS. (Mode is set by earliest of
/UCAS and /LCAS active edge and reset by the latest of /UCAS and /LCAS inactive edge.) However
write OPERATION and output High-Z control are done independently by each /UCAS, /LCAS.
ex) if /RAS = H to L, /UCAS = H, /LCAS = L, then /CAS-before-/RAS refresh cycle is selected.
Rev 0.1 / Apr'01
GM71V18163CJ-6E
DC Electrical Characteristics
(VCC = 3.3V+/-0.3V, Vss = 0V, TA = -30 ~ 85C)
Symbol
Parameter
Note
V
OH
V
OL
Output Level
Output "H" Level Voltage (I
OUT
=
-2mA
)
Unit
V
V
Max
V
CC
0.4
Min
2.4
0
Output Level
Output "L" Level Voltage (I
OUT
=
2
mA)
I
CC1
Operating Current
Average Power Supply Operating Current
(/RAS, /UCAS or /LCAS Cycling
:
t
RC
=
t
RC
min)
I
CC2
Standby Current (TTL)
Power Supply Standby Current
(/RAS, /UCAS, /LCAS = V
IH
,
D
OUT
=
High-Z)
I
CC3
RAS Only Refresh Current
Average Power Supply Current
RAS Only Refresh Mode
(t
RC
=
t
RC
min)
I
CC4
I
CC5
Standby Current (CMOS)
Power Supply Standby Current
(/RAS, /UCAS or /LCAS >= V
CC
- 0.2V, D
OUT
= High-Z)
I
CC6
/CAS-before-/RAS Refresh Current
(t
RC
=
t
RC
min)
I
CC7
I
L(I)
uA
10
-10
I
L(O)
uA
10
-10
Input Leakage Current
Any Input (0V
<=
V
IN
<=
4.6V)
Output Leakage Current
(D
OUT
is Disabled, 0V
<=
V
OUT
<= 4.
6V)
EDO Page Mode Current
Average Power Supply Current
EDO Page Mode
(t
HPC
= t
HPC
min)
Note: 1. I
CC
depends on output load condition when the device is selected.
I
CC
(max) is specified at the output open condition.
2. Address can be changed once or less while /RAS = V
IL
.
3. Address can be changed once or less while /LCAS and /UCAS = V
IH
.
4. /UCAS = L (<=0.2) and /LCAS = L (<=0.2) while /RAS = L (<=0.2).
Battery Back Up Operating Current(Standby with CBR Ref.)
(CBR refresh, t
RC
=125us
,
t
RAS
<=
0.3
us,
D
OUT
=
High-Z, CMOS interface)
400
-
4,5
uA
I
CC8
I
CC9
uA
Self-Refresh Mode Current
(/RAS, /UCAS or /LCAS<=0.2V
,
D
OUT
=
High-Z)
250
-
5
mA
2
-
mA
1
-
150
-
uA
mA
1, 2
mA
2
mA
1, 3
mA
5
-
5
1
mA
Standby Current /RAS = V
IH
/U
CAS, /LCAS = V
IL
D
OUT
=
Enable
60ns
170
-
60ns
170
-
60ns
165
-
60ns
-
170
Rev 0.1 / Apr'01
GM71V18163CJ-6E
Capacitance
(VCC = 3.3V+/-0.3V, TA = 25C)
Symbol
Parameter
Note
C
I1
C
I2
C
I/O
Input Capacitance (Address)
Input Capacitance (Clocks)
Output Capacitance (Data-In/Out)
1
1
1, 2
Unit
pF
Max
5
7
7
Min
-
-
-
Note: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. /UCAS and /LCAS = V
IH
to disable D
OUT
.
AC Characteristics
(VCC = 3.3V+/-0.3V, TA = -30 ~ +85C, Note 1, 2, 18, 19, 20)
Test Conditions
Input rise and fall times : 2 ns Output timing reference levels : 0.8V, 2.0V
Input levels : V
IL
= 0V, V
IH
= 3V
Output load : 1TTL gate + C
L
(100 pF)
Input timing reference levels : 0.8V, 2.0V
(Including scope and jig)
pF
pF
Read, Write, Read-Modify-Write and Refresh Cycles
(Common Parameters)
Symbol
Parameter
Note
Unit
Max
Min
t
RC
Random Read or Write Cycle Time
104
-
t
RP
/RAS Precharge Time
40
-
t
RAS
/RAS Pulse Width
60
10,000
t
CAS
/CAS Pulse Width
10,000
10
t
ASR
Row Address Set up Time
-
0
t
RAH
Row Address Hold Time
-
10
t
ASC
Column Address Set-up Time
-
0
t
CAH
Column Address Hold Time
-
10
t
RCD
/RAS to /CAS Delay Time
45
14
3
t
RAD
/RAS to Column Address Delay Time
30
12
4
t
RSH
/RAS Hold Time
-
13
t
CSH
/CAS Hold Time
-
40
t
CRP
/CAS to /RAS Precharge Time
-
5
t
T
Transition Time (Rise and Fall)
50
2
7
t
DZO
/OE Delay Time from D
IN
-
0
t
DZC
/CAS Delay Time from D
IN
-
0
/OE to D
IN
Delay Time
-
15
5
6
6
t
CP
/CAS Precharge Time
10
-
t
ODD
GM71V18163CJ-6E
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
21
21
22
23
Rev 0.1 / Apr'01
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