Document Outline
- Description
- Features
- Ordering Information
- Pin Configuration
- Pin Description
- Functional Block Diagram
- Absolute Maximum Ratings
- DC Operating Condition
- AC Operating Condition
- Capacitance
- Output Load Circuit
- DC Characteristics-I
- DC Characteristics-II
- AC Characteristics-I
- AC Characteristics-II
- Device Operating Option Table
- Command Truth Table
- Package Information
HY57V64820HGTP
4 Banks x 2M x 8Bit Synchronous DRAM
This document is a general product description and is subject to change without notice.Hynix Semiconductor does not assume any responsibility for use
of circuits described. No patent licenses are implied.
Rev. 0.1/ Nov. 03 1
DESCRIPTION
The Hynix HY57V64820HG is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the main memory applications which
require large memory density and high bandwidth. HY57V64820HG is organized as 4banks of 2,097,152x8.
HY57V64820HG is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchro-
nized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output
voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write cycles initiated by
a single control command (Burst length of 1,2,4,8 or Full page), and the burst count sequence(sequential or interleave). A burst of read
or write cycles in progress can be terminated by a burst terminate command or can be interrupted and replaced by a new burst read or
write command on any cycle. (This pipelined design is not restricted by a `2N` rule.)
FEATURES
Single 3.3
0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin
pitch
All inputs and outputs referenced to positive edge of system
clock
Data mask function by DQM
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Note) Hynix supports lead free part for each speed grade with same specification.
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V64820HGTP-5/55/6/7
200/183/166/143MHz
Normal
4Banks x 2Mbits x8
LVTTL
400mil 54pin TSOP II
(Pb free)
HY57V64820HGTP-K
133MHz
HY57V64820HGTP-H
133MHz
HY57V64820HGTP-8
125MHz
HY57V64820HGTP-P
100MHz
HY57V64820HGTP-S
100MHz
HY57V64820HGLTP-5/55/6/7
200/183/166/143MHz
Low power
HY57V64820HGLTP-K
133MHz
HY57V64820HGLTP-H
133MHz
HY57V64820HGLTP-8
125MHz
HY57V64820HGLTP-P
100MHz
HY57V64820HGLTP-S
100MHz
HY57V64820HGTP
Rev. 0.1/ Nov. 03 2
PIN CONFIGURATION
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the rising
edge of CLK
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one of the
states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A11
Address
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe, Write
Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ7
Data Input/Output
Multiplexed data input / output pin
VDD/VSS
Power Supply/Ground
Power supply for internal circuits and input buffers
VDDQ/VSSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
V
SS
DQ7
V
SSQ
NC
DQ6
V
DDQ
NC
DQ5
V
SSQ
NC
DQ4
V
DDQ
NC
V
SS
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
DD
DQ0
V
DDQ
NC
DQ1
V
SSQ
NC
DQ2
V
DDQ
NC
DQ3
V
SSQ
NC
V
DD
NC
/WE
/CAS
/RAS
/CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
54pin TSOP II
400mil x 875mil
0.8mm pin pitch
HY57V64820HGTP
Rev. 0.1/ Nov. 03 3
FUNCTIONAL BLOCK DIAGRAM
2Mbit x 4banks x 8 I/O Synchronous DRAM
St
at
e Ma
chin
e
A0
A1
A11
BA0
BA1
A
ddre
ss b
u
f
f
e
rs
Address
Registers
Mode Registers
Row
Pre
Decoders
Column
Pre
Decoders
Column Add
Counter
Row active
Column
Active
Burst
Counter
Data Out Control
CAS Latency
X deco
ders
Internal Row
counter
DQ0
DQ1
DQ6
DQ7
refresh
Self refresh logic
& timer
Pipe Line Control
I/O
Bu
ffe
r & L
o
g
ic
Bank Select
Sense
AMP &
I/O
Gate
CLK
CKE
CS
RAS
CAS
WE
DQM
X d
e
c
od
ers
X de
co
de
rs
Memory
Cell
Array
Y decoders
X deco
ders
2Mx8 Bank 1
2Mx8 Bank 0
2Mx8 Bank 2
2Mx8 Bank3
HY57V64820HGTP
Rev. 0.1/ Nov. 03
4
ABSOLUTE MAXIMUM RATINGS
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION
(TA=0 to 70
C
)
Note :
1.All voltages are referenced to V
SS
= 0V
2.V
IH
(max) is acceptable 5.6V AC pulse width with
3ns of duration
3.V
IL
(min) is acceptable -2.0V AC pulse width with
3ns of duration
AC OPERATING CONDITION
(TA=0 to 70
C
, V
DD
=3.3
0.3V, V
SS
=0V)
Note :
1. Output load to measure access time is equivalent to two TTL gates and one capacitor (50pF)
For details, refer to AC/DC output circuit
Parameter
Symbol
Rating
Unit
Ambient Temperature
T
A
0 ~ 70
C
Storage Temperature
T
STG
-55 ~ 125
C
Voltage on Any Pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
DD
relative to V
SS
V
DD,
V
DDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
I
OS
50
mA
Power Dissipation
P
D
1
W
Soldering Temperature
Time
T
SOLDER
260
10
C
Sec
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
V
DD
, V
DDQ
3.0
3.3
3.6
V
1
Input High Voltage
V
IH
2.0
3.0
V
DDQ
+ 2.0
V
1,2
Input Low Voltage
V
IL
V
SSQ
- 2.0
0
0.8
V
1,3
Parameter
Symbol
Value
Unit
Note
AC Input High / Low Level Voltage
V
IH
/ V
IL
2.4/0.4
V
Input Timing Measurement Reference Level Voltage
Vtrip
1.4
V
Input Rise / Fall Time
tR / tF
1
ns
Output Timing Measurement Reference Level
Voutref
1.4
V
Output Load Capacitance for Access Time Measurement
CL
50
pF
1
HY57V64820HGTP
Rev. 0.1/ Nov. 03
5
CAPACITANCE
(TA=25
C
, f=1MHz)
OUTPUT LOAD CIRCUIT
DC CHARACTERISTICS I
(TA=0 to 70
C
, V
DD
=3.3
0.3V)
Note :
1.V
IN
= 0 to 3.6V, All other pins are not tested under V
IN
=0V
2.D
OUT
is disabled, V
OUT
=0 to 3.6V
Parameter
Pin
Symbol
Min
Max
Unit
Input capacitance
CLK
C
I1
2
4
pF
A0 ~ A11, BA0, BA1, CKE, CS, RAS, CAS,
WE, DQM
CI
2
2.5
5
pF
Data input / output capacitance
DQ0 ~ DQ7
C
I/O
2
6.5
pF
Parameter
Symbol
Min.
Max
Unit
Note
Input Leakage Current
I
LI
-1
1
uA
1
Output Leakage Current
I
LO
-1
1
uA
2
Output High Voltage
V
OH
2.4
-
V
I
OH
= -4mA
Output Low Voltage
V
OL
-
0.4
V
I
OL
= +4mA
Vtt=1.4V
RT=250
50pF
Output
50pF
Output
DC Output Load Circuit
AC Output Load Circuit
HY57V64820HGTP
Rev. 0.1/ Nov. 03
6
DC CHARACTERISTICS II
(TA=0 to 70
C
, V
DD
=3.3
0.3V, V
SS
=0V)
Note :
1.I
DD1
and I
DD4
depend on output loading and cycle rates. Specified values are measured with the output open
2.Min. of tRRC (Refresh RAS cycle time) is shown at AC CHARACTERISTICS II
3.HY57V64820HGTP-7/K/H/8/P/S
4.HY57V64820HGLTP-7/K/H/8/P/S
Parameter
Symbol
Test Condition
Speed
Unit
Note
-6
-7
-K
-H
-8
-P/S
Operating Current
I
DD1
Burst length=1, One bank active
t
RC
t
RC
(min), I
OL
=0mA
90
85
85
85
85
80
mA
1
Precharge Standby Current
in Power Down Mode
I
DD2P
CKE
V
IL
(max), t
CK
= min
2
mA
I
DD2PS
CKE
V
IL
(max), t
CK
=
2
mA
Precharge Standby Current
in Non Power Down Mode
I
DD2N
CKE
V
IH
(min), CS
V
IH
(min), t
CK
= min
Input signals are changed one time during
2clks. All other pins
V
DD
-0.2V or
0.2V
15
mA
I
DD2NS
CKE
V
IH
(min), t
CK
=
Input signals are stable.
12
mA
Active Standby Current
in Power Down Mode
I
DD3P
CKE
V
IL
(max), t
CK
= min
6
mA
I
DD3PS
CKE
V
IL
(max), t
CK
=
5
mA
Active Standby Current
in Non Power Down Mode
I
DD3N
CKE
V
IH
(min), CS
V
IH
(min), t
CK
= min
Input signals are changed one time during
2clks. All other pins
V
DD
-0.2V or
0.2V
30
mA
I
DD3NS
CKE
V
IH
(min), t
CK
=
Input signals are stable.
20
mA
Burst Mode Operating
Current
I
DD4
t
CK
t
CK
(min), I
OL
=0mA
All banks active
CL=3
150
150
150
150
130
120
mA
1
CL=2
NA
NA
120
mA
Auto Refresh Current
I
DD5
t
RRC
t
RRC
(min), All banks active
160
mA
2
Self Refresh Current
I
DD6
CKE
0.2V
1
mA
3
400
uA
4
HY57V64820HGTP
Rev. 0.1/ Nov. 03
7
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Note :
1.Assume tR / tF (input rise and fall time ) is 1ns
2.Access times to be measured with input signals of 1v/ns edge rate
Parameter
Symbol
-6
-7
-K
-H
-8
-P
-S
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
System clock
cycle time
CAS
Latency = 3
tCK3
6
1000
7
1000
7.5
1000
7.5
1000
8
1000
10
1000
10
1000
ns
CAS
Latency = 2
tCK2
10
10
7.5
10
10
10
12
ns
Clock high pulse width
tCHW
2.5
-
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
Clock low pulse width
tCLW
2.5
-
2.5
-
2.5
-
2.5
-
3
-
3
-
3
-
ns
1
Access time
from clock
CAS
Latency = 3
tAC3
-
5.4
-
5.4
-
5.4
5.4
-
6
6
-
6
ns
2
CAS
Latency = 2
tAC2
-
6
-
6
-
5.4
6
-
6
-
6
-
8
ns
Data-out hold time
tOH
2.7
-
2.7
-
2.7
-
2.7
-
3
-
3
-
3
-
ns
Data-Input setup time
tDS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Data-Input hold time
tDH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Address setup time
tAS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Address hold time
tAH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CKE setup time
tCKS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
CKE hold time
tCKH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
Command setup time
tCS
1.5
-
1.5
-
1.5
-
1.5
-
2
-
2
-
2
-
ns
1
Command hold time
tCH
0.8
-
0.8
-
0.8
-
0.8
-
1
-
1
-
1
-
ns
1
CLK to data output in
low Z-time
tOLZ
1
-
1.5
-
1.5
-
1.5
-
1
-
1
-
2
-
ns
CLK to data
output in high
Z-time
CAS
Latency = 3
tOHZ3
5.4
5.4
5.4
5.4
6
6
6
ns
CAS
Latency = 2
tOHZ2
ns
HY57V64820HGTP
Rev. 0.1/ Nov. 03
8
AC CHARACTERISTICS II
Note :
1. A new command can be given tRRC after self refresh exit
Parameter
Symbol
-6
-7
-K
-H
-8
-P
-S
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
RAS Cycle
Time
Operation
t
RC
60
-
62
-
65
-
65
-
68
-
70
-
70
-
ns
Auto
Refresh
t
RRC
60
-
62
-
65
-
65
-
68
-
70
-
70
-
ns
RAS to CAS Delay
t
RCD
18
-
20
-
15
-
20
-
20
-
20
-
20
-
ns
RAS Active Time
t
RAS
42
100K
42
120K
45
120K
45
120K
48
120K
50
120K
50
120K
ns
RAS Precharge Time
t
RP
18
-
20
-
15
-
20
-
20
-
20
-
20
-
ns
RAS to RAS Bank Active
Delay
t
RRD
12
-
14
-
15
-
15
-
16
-
20
-
20
-
ns
CAS to CAS Delay
t
CCD
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Write Command to Data-
In Delay
t
WTL
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
Data-In to Precharge
Command
t
DPL
2
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Data-In to Active
Command
t
DAL
5
-
4
-
4
-
4
-
4
-
3
-
3
-
CLK
DQM to Data-Out Hi-Z
t
DQZ
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
DQM to Data-In Mask
t
DQM
0
-
0
-
0
-
0
-
0
-
0
-
0
-
CLK
MRS to New Command
t
MRD
2
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Precharge
to Data
Output Hi-Z
CAS
Latency = 3
t
PROZ3
3
-
3
-
3
-
3
-
3
-
3
-
3
-
CLK
CAS
Latency = 2
t
PROZ2
2
-
2
-
2
-
2
-
2
-
2
-
2
-
CLK
Power Down Exit Time
t
PDE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
Self Refresh Exit Time
t
SRE
1
-
1
-
1
-
1
-
1
-
1
-
1
-
CLK
1
Refresh Time
t
REF
-
64
-
64
-
64
-
64
-
64
-
64
-
64
ms
HY57V64820HGTP
Rev. 0.1/ Nov. 03
9
DEVICE OPERATING OPTION TABLE
HYHY57V64820(L)TP-6
57V64820HG(L)TP-7
HY57V64820HG(L)TP-K
HY57V64820HG(L)TP-H
HY57V64820HG(L)TP-8
HY57V64820HG(L)TP-P
HY57V64820HG(L)TP-S
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
166MHz(6ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
5.4ns
2.7ns
143MHz(7ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
133MHz(7.5ns)
2CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
143MHz(7ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
133MHz(7.5ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
2CLKs
2CLKs
6CLKs
8CLKs
2CLKs
5.4ns
2.7ns
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
133MHz(7.5ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
5.4ns
2.7ns
125MHz(8ns)
3CLKs
3CLKs
6CLKs
9CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
125MHz(8ns)
3CLKs
3CLKs
7CLKs
10CLKs
3CLKs
6ns
3ns
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
83MHz(12ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
83MHz(12ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
66MHz(15ns)
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
6ns
3ns
CAS Latency
tRCD
tRAS
tRC
tRP
tAC
tOH
100MHz(10ns)
3CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
83MHz(12ns)
2CLKs
2CLKs
5CLKs
7CLKs
2CLKs
6ns
3ns
66MHz(15ns)
2CLKs
2CLKs
4CLKs
6CLKs
2CLKs
6ns
3ns
HY57V64820HGTP
Rev. 0.1/ Nov. 03
10
COMMAND TRUTH TABLE
Note :
1. Exiting Self Refresh occurs by asynchronously bringing CKE from low to high
2. X = Don
t care, H = Logic High, L = Logic Low. BA =Bank Address, RA = Row Address, CA = Column Address,
Opcode = Operand Code, NOP = No Operation
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
ADDR
A10/
AP
BA
Note
Mode Register Set
H
X
L
L
L
L
X
OP code
No Operation
H
X
H
X
X
X
X
X
L
H
H
H
Bank Active
H
X
L
L
H
H
X
RA
V
Read
H
X
L
H
L
H
X
CA
L
V
Read with Autoprecharge
H
Write
H
X
L
H
L
L
X
CA
L
V
Write with Autoprecharge
H
Precharge All Banks
H
X
L
L
H
L
X
X
H
X
Precharge selected Bank
L
V
Burst Stop
H
X
L
H
H
L
X
X
DQM
H
X
V
X
Auto Refresh
H
H
L
L
L
H
X
X
Burst-READ-Single-WRITE
H
X
L
L
L
L
X
A9 Pin High
(Other Pins OP code)
Self Refresh
1
Entry
H
L
L
L
L
H
X
X
Exit
L
H
H
X
X
X
X
L
H
H
H
Precharge power
down
Entry
H
L
H
X
X
X
X
X
L
H
H
H
Exit
L
H
H
X
X
X
X
L
H
H
H
Clock
Suspend
Entry
H
L
H
X
X
X
X
X
L
V
V
V
Exit
L
H
X
X
HY57V64820HGTP
Rev. 0.1/ Nov. 03
11
PACKAGE INFORMATION
400mil 54pin Thin Small Outline Package
11.938(0.4700)
11.735(0.4620)
10.262(0.4040)
10.058(0.3960)
22.327(0.8790)
22.149(0.8720)
5deg
0deg
0.597(0.0235)
0.406(0.0160)
0.210(0.0083)
0.120(0.0047)
1.194(0.0470)
0.991(0.0390)
0.80(0.0315)BSC
0.400(0.016)
0.300(0.012)
UNIT : mm(inch)
0.150(0.0059)
0.050(0.0020)
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