HY57V653220B(L)TC-I(0.9).fm
HY57V653220B
4 Banks x 512K x 32Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.9 / Apr. 2003
DESCRIPTION
The Hynix HY57V653220B is a 67,108,864-bit CMOS Synchronous DRAM, ideally suited for the Mobile applications
which require low power consumption and extended temperature range. HY57V653220B is organized as 4banks of
524,288x32.
HY57V653220B is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and out-
puts are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
JEDEC standard 3.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 86pin TSOP-II with 0.5mm of
pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM0,1,2 and 3
Internal four banks operation
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
Burst Read Single Write operation
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V653220BTC-6I
166MHz
Normal
4Banks x 512Kbits
x32
LVTTL
400mil 86pin TSOP II
HY57V653220BTC-7I
143MHz
HY57V653220BTC-10I
100MHz
HY57V653220BLTC-6I
166MHz
HY57V653220BLTC-7I
143MHz
HY57V653220BLTC-10I
100MHz
Rev. 0.9 / Apr. 2003 2
HY57V653220B
PIN CONFIGURATION
PIN DESCRIPTION
PIN
PIN NAME
DESCRIPTION
CLK
Clock
The system clock input. All other inputs are registered to the SDRAM on the
rising edge of CLK.
CKE
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM will be one
of the states among power down, suspend or self refresh
CS
Chip Select
Enables or disables all inputs except CLK, CKE and DQM
BA0, BA1
Bank Address
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
A0 ~ A10
Address
Row Address : RA0 ~ RA10, Column Address : CA0 ~ CA7
Auto-precharge flag : A10
RAS, CAS, WE
Row Address Strobe,
Column Address Strobe,
Write Enable
RAS, CAS and WE define the operation
Refer function truth table for details
DQM0~3
Data Input/Output Mask
Controls output buffers in read mode and masks input data in write mode
DQ0 ~ DQ31
Data Input/Output
Multiplexed data input / output pin
V
DD
/V
SS
Power Supply/Ground
Power supply for internal circuits and input buffers
V
DDQ
/V
SSQ
Data Output Power/Ground
Power supply for output buffers
NC
No Connection
No connection
V
D D
D Q 0
V
D D Q
D Q 1
D Q 2
V
S S Q
D Q 3
D Q 4
V
D D Q
D Q 5
D Q 6
V
S S Q
D Q 7
N C
V
D D
D Q M 0
/W E
/C A S
/R A S
/C S
N C
B A 0
B A 1
A 1 0/A P
A 0
A 1
A 2
D Q M 2
V
D D
N C
D Q 16
V
S S Q
D Q 17
D Q 18
V
D D Q
D Q 19
D Q 20
V
S S Q
D Q 21
D Q 22
V
D D Q
D Q 23
V
D D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
V
S S
D Q 15
V
S S Q
D Q 14
D Q 13
V
D D Q
D Q 12
D Q 11
V
S S Q
D Q 10
D Q 9
V
D D Q
D Q 8
N C
V
S S
D Q M 1
N C
N C
C LK
C K E
A 9
A 8
A 7
A 6
A 5
A 4
A 3
D Q M 3
V
S S
N C
D Q 31
V
D D Q
D Q 30
D Q 29
V
S S Q
D Q 28
D Q 27
V
D D Q
D Q 26
D Q 25
V
S S Q
D Q 24
V
S S
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
8 6 p in T S O P II
4 0 0 m il x 8 7 5 m il
0 .5 m m p in p itc h
Rev. 0.9 / Apr. 2003 3
HY57V653220B
FUNCTIONAL BLOCK DIAGRAM
512Kbit x 4banks x 32 I/O Synchronous DRAM
X deco
ders
St
at
e Ma
chin
e
A0
A1
A10
BA0
BA1
A
ddre
ss b
u
f
f
e
rs
Address
Register
M ode Registers
Row
Pre
Decoders
Colum n
Pre
Decoders
Colum n Add
Counter
Row Active
Colum n
Active
Burst
Counter
Data O ut Control
CAS Latency
Internal Row
Counter
DQ 0
DQ 1
DQ 30
DQ 31
Self Refresh Logic
& Tim er
Pipe Line Control
I/
O Bu
ffe
r &
Lo
gic
Bank Select
Sense AMP
& I/O Gate
CLK
CKE
CS
RAS
CAS
W E
DQ M 0
DQ M 1
DQ M 2
DQ M 3
512Kx32 Bank 3
X de
code
rs
X d
e
co
ders
M em ory
Cell
Array
Y decoders
X d
e
c
od
ers
512Kx32 Bank 0
512Kx32 Bank 1
512Kx32 Bank 2
Rev. 0.9 / Apr. 2003
4
HY57V653220B
ABSOLUTE MAXIMUM RATINGS
Note :
Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITION
(TA= -40 to 85
C
)
Note :
1.All voltages are referenced to V
SS
= 0V
2.V
IH
(max) is acceptable 5.6V AC pulse width with
3ns of duration with no input clamp diodes
3.V
IL
(min) is acceptable -2.0V AC pulse width with
3
ns of duration with no input clamp diodes
AC OPERATING CONDITION
(TA= -40 to 85
C
, 3.0V
V
DD
3.6V, V
SS
=0V - Note1)
Note :
1.Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF)
For details, refer to AC/DC output load circuit
Parameter
Symbol
Rating
Unit
Ambient Temperature
T
A
-40 ~ 85
C
Storage Temperature
T
STG
-55 ~ 125
C
Voltage on Any Pin relative to V
SS
V
IN
, V
OUT
-1.0 ~ 4.6
V
Voltage on V
DD
relative to V
SS
V
DD,
V
DDQ
-1.0 ~ 4.6
V
Short Circuit Output Current
I
OS
50
mA
Power Dissipation
P
D
1
W
Soldering Temperature
Time
T
SOLDER
260
10
C
Sec
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
V
DD
, V
DDQ
3.0
3.3
3.6
V
1,2
Input high voltage
V
IH
2.0
3.0
V
DDQ
+ 0.3
V
1,3
Input low voltage
V
IL
V
SSQ
- 0.3
0
0.8
V
1,4
Parameter
Symbol
Value
Unit
Note
AC input high / low level voltage
V
IH
/ V
IL
2.4/0.4
V
Input timing measurement reference level voltage
Vtrip
1.4
V
Input rise / fall time
tR / tF
1
ns
Output timing measurement reference level
Voutref
1.4
V
Output load capacitance for access time measurement
CL
30
pF
1
Rev. 0.9 / Apr. 2003
5
HY57V653220B
CAPACITANCE
(TA=25
C
, f=1MHz, VDD=3.3V)
OUTPUT LOAD CIRCUIT
DC CHARACTERISTICS I
(DC operating conditions unless otherwise noted)
Note :
1.V
IN
= 0 to 3.6V, All other pins are not under test = 0V
2.D
OUT
is disabled, V
OUT
=0 to 3.6V
Parameter
Pin
Symbol
Min
Max
Unit
Input capacitance
CLK
C
I1
2.5
4
pF
A0 ~ A10, BA0, BA1, CKE, CS, RAS,
CAS, WE, DQM0~3
CI
2
2.5
5
pF
Data input / output capacitance
DQ0 ~ DQ31
C
I/O
4
6.5
pF
Parameter
Symbol
Min.
Max
Unit
Note
Input leakage current
I
LI
-1
1
uA
1
Output leakage current
I
LO
-1.5
1.5
uA
2
Output high voltage
V
OH
2.4
-
V
I
OH
= -2mA
Output low voltage
V
OL
-
0.4
V
I
OL
= +2mA
Vtt=1.4V
RT=500
30pF
Output
DC Output Load Circuit
AC Output Load Circuit
Vtt=1.4V
RT=50
30pF
Output
Z0 = 50
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