8Mx64 bits
PC100 SDRAM SO DIMM
based on 4Mx16 SDRAM with LVTTL, 4 banks & 4K Refresh
HYM7V65801B Q-Series
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not
assume any responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.3/Dec. 01
1
DESCRIPTION
The Hynix HYM7V65801B Q-Series are 8Mx64bits Synchronous DRAM Modules. The modules are composed of eight
4Mx16bits CMOS Synchronous DRAMs in 400mil 54pin TSOP-II package and 2Kbit EEPROM in 8pin TSSOP package
on a 144pin glass-epoxy printed circuit board. Three 0.1uF decoupling capacitors per each SDRAM are mounted on the
PCB.
The HYM7V65801B Q-Series are Small Outline Dual In-line Memory Modules suitable for easy interchange and addition
of 64Mbytes memory. The HYM7V65801B Q-Series are offering fully synchronous operation referenced to a positive
edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are
internally pipelined to achieve very high bandwidth.
FEATURES
PC100MHz support
144pin SDRAM SO DIMM
Serial Presence Detect with EEPROM
1.25" (31.75mm) Height PCB with Double Sided
components
Single 3.3 0.3V power supply
All devices pins are compatible with LVTTL interface
Data mask function by DQM
SDRAM internal banks : four banks
Module banks : two physical banks
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
-. 1, 2, 4, 8, or Full Page for Sequential Burst
-. 1, 2, 4 or 8 for Interleave Burst
Programmable /CAS Latency
-. 2, 3 clocks
ORDERING INFORMATION
PART NO.
MAX.
FREQUENCY
INTERNAL
BANK
REF.
POWER
SDRAM
PACKAGE
PLATING
HYM7V65801BTQG-8 125MHz
HYM7V65801BTQG-10P 100MHz
HYM7V65801BTQG-10S 100MHz
Normal
HYM7V65801BLTQG-8 125MHz
HYM7V65801BLTQG-10P 100MHz
HYM7V65801BLTQG-10S 100MHz
4 Banks
4K
Low Power
TSOP-II Gold
PC100 SDRAM SO DIMM
HYM7V65801B Q-Series
Rev. 1.3/Dec. 01
2
PIN DESCRIPTION
PIN NAME
DESCRIPTION
CK0, CK1
Clock Inputs
The System Clock Input. All other inputs are registered to the
SDRAM on the rising edge of CLK.
CKE0, CKE1
Clock Enable
Controls internal clock signal and when deactivated, the SDRAM
will be one of the states among power down, suspend or self
refresh.
/S0, /S1
Chip Select
Enables or disables all inputs except CK, CKE and DQM.
BA0, BA1
SDRAM Bank Address
Select bank to be activated during /RAS activity.
Select bank to be read/written during /CAS activity
A0~A11 Address
Inputs
Row address : RA0~RA11, Column address : CA0~CA7
Auto-precharge flag : A10
/RAS
Row Address Strobe
/RAS define the operation.
Refer to the function truth table for details.
/CAS
Column Address Strobe
/CAS define the operation.
Refer to the function truth table for details.
/WE Write
Enable
/WE define the operation.
Refer to the function truth table for details.
DQM0~DQM7
Data Input/Output Mask
Controls output buffers in read mode and masks input data in
write mode.
DQ0~DQ63
Data Input/Output
Multiplexed data input/output pins
VCC
Power Supply (3.3V)
Power supply for internal circuits and input/output buffers
VSS Ground
Ground
SCL
SPD Clock Input
Serial Presence Detect Clock Input
SDA
SPD Data Input/Output
Serial Presence Detect Data input/output
NC
No Connect
No Connect or Don't Use
PC100 SDRAM SO DIMM
HYM7V65801B Q-Series
Rev. 1.3/Dec. 01
3
PIN ASSIGNMENTS
FRONT SIDE
BACK SIDE
FRONT SIDE
BACK SIDE
PIN NO.
NAME
PIN NO.
NAME
PIN NO.
NAME
PIN NO.
NAME
1 VSS 2 VSS 71 /S1 72 NC
3 DQ0 4 DQ32
73 NC 74 CK1
5 DQ1 6 DQ33 75 VSS 76 VSS
7 DQ2 8 DQ34
77 NC 78 NC
9 DQ3 10
DQ35
79 NC 80 NC
11 VCC 12 VCC 81 VCC 82 VCC
13 DQ4 14 DQ36 83 DQ16 84 DQ48
15 DQ5 16 DQ37 85 DQ17 86 DQ49
17 DQ6 18 DQ38 87 DQ18 88 DQ50
19 DQ7 20 DQ39 89 DQ19 90 DQ51
21 VSS 22 VSS 91 VSS 92 VSS
23 DQM0 24 DQM4 93 DQ20 94 DQ52
25 DQM1 26 DQM5 95 DQ21 96 DQ53
27 VCC 28 VCC 97 DQ22 98 DQ54
29 A0 30 A3 99
DQ23
100
DQ55
31 A1 32 A4 101 VCC 102 VCC
33 A2 34 A5 103 A6 104 A7
35 VSS 36 VSS 105 A8 106 BA0
37 DQ8 38 DQ40 107 VSS 108 VSS
39 DQ9 40 DQ41
109 A9 110 BA1
41 DQ10 42 DQ42 111
A10/AP
112 A11
43 DQ11 44 DQ43 113 VCC 114 VCC
45 VCC 46 VCC 115 DQM2 116 DQM6
47 DQ12 48 DQ44 117 DQM3 118 DQM7
49 DQ13 50 DQ45 119 VSS 120 VSS
51 DQ14 52 DQ46 121 DQ24 122 DQ56
53 DQ15 54 DQ47 123 DQ25 124 DQ57
55 VSS 56 VSS 125 DQ26
126 DQ58
57 NC 58 NC 127
DQ27
128
DQ59
59 NC 60 NC 129 VCC 130 VCC
131 DQ28 132 DQ60
Voltage Key
133 DQ29 134 DQ61
61 CK0 62 CKE0 135 DQ30 136 DQ62
63 VCC 64 VCC 137 DQ31 138 DQ63
65 /RAS 66 /CAS 139 VSS 140 VSS
67 /WE 68 CKE1 141 SDA 142 SCL
69 /S0 70 NC 143 VCC 144 VCC
PC100 SDRAM SO DIMM
HYM7V65801B Q-Series
Rev. 1.3/Dec. 01
4
BLOCK DIAGRAM
Note : The serial resistor values of DQs are 10 Ohms.
PC100 SDRAM SO DIMM
HYM7V65801B Q-Series
Rev. 1.3/Dec. 01
5
SERIAL PRESENCE DETECT
BYTE
FUNCTION
FUNCTION
VALUE
NUMBER
DESCRIBED
-8
-10P
-10S
-8
-10P
-10S
NOTE
BYTE0
# of Bytes Written into Serial Memory
at Module Manufacturer
128 Bytes
80h
BYTE1
Total # of Bytes of SPD Memory Device
256 Bytes
08h
BYTE2
Fundamental Memory Type
SDRAM
04h
BYTE3
# of Row Addresses on This Assembly
12
0Ch
1
BYTE4
# of Column Addresses on This Assembly
8
08h
BYTE5
# of Module Banks on This Assembly
2 Banks
02h
BYTE6
Data Width of This Assembly
64 Bits
40h
BYTE7
Data Width of This Assembly (Continued)
-
00h
BYTE8
Voltage Interface Standard of This Assembly
LVTTL
01h
BYTE9
SDRAM Cycle Time @ /CAS Latency=3
8ns
10ns
10ns
80h
A0h
A0h
BYTE10
Access Time from Clock @ /CAS Latency=3
6ns
6ns
6ns
60h
60h
60h
BYTE11
DIMM Configuration Type
None
00h
BYTE12 Refresh
Rate/Type
15.625
s
/ Self Refresh Supported
80h
BYTE13
Primary SDRAM Width
x16
10h
BYTE14
Error Checking SDRAM Width
None
00h
BYTE15
Minimum Clock Delay Back to Back Random
Column Address
tCCD = 1 CLK
01h
BYTE16
Burst Lengths Supported
1,2,4,8,Full Page
8Fh
2
BYTE17
# of Banks on Each SDRAM Device
4 Banks
04h
BYTE18
SDRAM Device Attributes, CAS # Latency
/CAS Latency=2,3
06h
BYTE19
SDRAM Device Attributes, CS # Latency
/CS Latency=0
01h
BYTE20
SDRAM Device Attributes, Write Latency
/WE Latency=0
01h
BYTE21
SDRAM Module Attributes
Neither Buffered nor Registered
00h
BYTE22
SDRAM Device Attributes, General
+/-10% voltage tolerance, Burst
Read Single bit Write, Precharge
All, Auto Precharge, Early RAS
Precharge
0Eh
BYTE23
SDRAM Cycle Time @ /CAS Latency=2
10ns
10ns
12ns
A0h
A0h
C0h
BYTE24
Access Time from Clock @ /CAS Latency=2
6ns
6ns
6ns
60h
60h
60h
BYTE25
SDRAM Cycle Time @ /CAS Latency=1
-
-
-
00h
00h
00h
BYTE26
Access Time from Clock @ /CAS Latency=1
-
-
-
00h
00h
00h
BYTE27
Minimum Row Precharge Time (tRP)
20ns
20ns
20ns
14h
14h
14h
BYTE28
Minimum Row Active to Row Active Delay (tRRD)
16ns
20ns
20ns
10h
14h
14h
BYTE29
Minimum /RAS to /CAS Delay (tRCD)
20ns
20ns 20ns 14h 14h 14h
BYTE30
Minimum /RAS Pulse width (tRAS)
48ns
50ns
50ns
30h
32h
32h
BYTE31
Module Bank Density
32MB
08h
BYTE32
Command and Address Signal Input Setup Time
2ns
2ns
2ns
20h
20h
20h
BYTE33
Command and Address Signal Input Hold Time
1ns
1ns
1ns
10h
10h
10h
BYTE34
Data Signal Input Setup Time
2ns
2ns
2ns
20h
20h
20h
BYTE35
Data Signal Input Hold Time
1ns
1ns
1ns
10h
10h
10h
BYTE36
61
Superset Information (may be used in future)
-
00h
BYTE62
SPD Revision
Intel SPD 1.2A
12h
3, 8
BYTE63
Checksum for Bytes 0~62
-
DFh
05h
25h
BYTE64
Manufacturer JEDEC ID Code
Hynix JEDEC ID
ADh
BYTE65
~71
....Manufacturer JEDEC ID Code
Unused
FFh
BYTE72 Manufacturing
Location
Hynix (Korea Area)
HSA (United States Area)
HSU (Europe Area)
HSJ (Japan Area)
HSS (Singapore)
Asia Area
0*h
1*h
2*h
3*h
4*h
5*h
9
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