This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.5/May. 02 1
16Mx72 bits
Registered DDR SDRAM DIMM
HYMD116G725A(L)8-K/H/L
DESCRIPTION
Hynix HYMD116G725A(L)8-K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line
Memory Modules (DIMMs) which are organized as 16Mx72 high-speed memory arrays. Hynix HYMD116G725A(L)8-
K/H/L series consists of nine 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate.
Hynix HYMD116G725A(L)8-K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of
industry standard. It is suitable for easy interchange and addition.
Hynix HYMD116G725A(L)8-K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous
operations referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs
are latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both ris-
ing and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth.
All input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and
burst lengths allow variety of device operation in high performance memory system.
Hynix HYMD116G725A(L)8-K/H/L series incorporates SPD(serial presence detect). Serial presence detect function is
implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify
DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.
FEATURES
ORDERING INFORMATION
Part No.
Power Supply
Clock Frequency
Interface
Form Factor
HYMD116G725A(L)8-K
V
DD
=2.5V
V
DDQ
=2.5V
133MHz (*DDR266A)
SSTL_2
184pin Registered DIMM
5.25 x 1.7 x 0.15 inch
HYMD116G725A(L)8-H
133MHz (*DDR266B)
HYMD116G725A(L)8-L
100MHz (*DDR200)
128MB (16M x 72) Registered DDR DIMM based on
16Mx8 DDR SDRAM
JEDEC Standard 184-pin dual in-line memory mod-
ule (DIMM)
Error Check Correction (ECC) Capability
Registered inputs with one-clock delay
Phase-lock loop (PLL) clock driver to reduce loading
2.5V +/- 0.2V VDD and VDDQ Power supply
All inputs and outputs are compatible with SSTL_2
interface
Fully differential clock operations (CK & /CK) with
100MHz/125MHz/133MHz
Programmable CAS Latency 2 / 2.5 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal four bank operations with single pulsed RAS
Auto refresh and self refresh supported
4096 refresh cycles / 64ms
* JEDEC Defined Specifications compliant
HYMD116G725A(L)8-K/H/L
Rev. 0.5/May. 02 2
PIN DESCRIPTION
PIN ASSIGNMENT
Pin
Pin Description
Pin
Pin Description
CK0, /CK1
Differential Clock Inputs
VDDQ
DQs Power Supply
/CS0
Chip Select Input
VSS
Ground
CKE0
Clock Enable Input
VREF
Reference Power Supply
/RAS, /CAS, /WE
Commend Sets Inputs
VDDSPD
Power Supply for SPD
A0 ~ A11
Address
SA0~SA2
E
2
PROM Address Inputs
BA0, BA1
Bank Address
SCL
E
2
PROM Clock
DQ0~DQ63
Data Inputs/Outputs
SDA
E
2
PROM Data I/O
CB0~CB7
Data Strobe Inputs/Outputs
WP
Write Protect Flag
DQS0~DQS8
Data Strobe Inputs/Outputs
VDDID
VDD Identification Flag
DM0~8
Data-in Mask
DU
Do not Use
VDD
Power Supply
NC
No Connection
/RESET
Reset Enable
FETEN
FET Enable
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
VREF
32
A5
62
VDDQ
93
VSS
124
VSS
154
/RAS
2
DQ0
33
DQ24
63
/WE
94
DQ4
125
A6
155
DQ45
3
VSS
34
VSS
64
DQ41
95
DQ5
126
DQ28
156
VDDQ
4
DQ1
35
DQ25
65
/CAS
96
VDDQ
127
DQ29
157
/CS0
5
DQS0
36
DQS3
66
VSS
97
DM0
128
VDDQ
158
/CS1*
6
DQ2
37
A4
67
DQS5
98
DQ6
129
DM3
159
DM5
7
VDD
38
VDD
68
DQ42
99
DQ7
130
A3
160
VSS
8
DQ3
39
DQ26
69
DQ43
100
VSS
131
DQ30
161
DQ46
9
NC
40
DQ27
70
VDD
101
NC
132
VSS
162
DQ47
10
/RESET
41
A2
71
NC
102
NC
133
DQ31
163
NC
11
VSS
42
Vss
72
DQ48
103
A13*
134
CB4
164
VDDQ
12
DQ8
43
A1
73
DQ49
104
VDDQ
135
CB5
165
DQ52
13
DQ9
44
CB0
74
VSS
105
DQ12
136
VDDQ
166
DQ53
14
DQS1
45
CB1
75
DU
106
DQ13
137
CK0
167
NC, FETEN*
15
VDDQ
46
VDD
76
DU
107
DM1
138
/CK0
168
VDD
16
DU
47
DQS8
77
VDDQ
108
VDD
139
VSS
169
DM6
17
DU
48
A0
78
DQS6
109
DQ14
140
DM8
170
DQ54
18
VSS
49
CB2
79
DQ50
110
DQ15
141
A10
171
DQ55
19
DQ10
50
VSS
80
DQ51
111
CKE1*
142
CB6
172
VDDQ
20
DQ11
51
CB3
81
VSS
112
VDDQ
143
VDDQ
173
NC
21
CKE0
52
BA1
82
VDDID
113
BA2*
144
CB7
174
DQ60
22
VDDQ
Key
83
DQ56
114
DQ20
key
175
DQ61
23
DQ16
53
DQ32
84
DQ57
115
A12*
145
VSS
176
VSS
24
DQ17
54
VDDQ
85
VDD
116
VSS
146
DQ36
177
DM7
25
DQS2
55
DQ33
86
DQS7
117
DQ21
147
DQ37
178
DQ62
26
VSS
56
DQS4
87
DQ58
118
A11
148
VDD
179
DQ63
27
A9
57
DQ34
88
DQ59
119
DM2
149
DM4
180
VDDQ
28
DQ18
58
VSS
89
VSS
120
VDD
150
DQ38
181
SA0
29
A7
59
BA0
90
WP
121
DQ22
151
DQ39
182
SA1
30
VDDQ
60
DQ35
91
SDA
122
A8
152
VSS
183
SA2
31
DQ19
61
DQ40
92
SCL
123
DQ23
153
DQ44
184
VDDSPD
* These are not used on this module but may be used for other module in 184pin DIMM family
HYMD116G725A(L)8-K/H/L
Rev. 0.5/May. 02 3
FUNCTIONAL BLOCK DIAGRAM
D0
/CS
DM
DM0
DQS
DQS0
D1
/CS
DM
DM1
DQS
DQS1
D2
/CS
DM
DM2
DQS
DQS2
/CS
DM
DM3
D3
DQS
DQS3
D4
CS
DM
DM4
DQS
D5
/CS
DM
DM5
DQS
DQS5
D6
/CS
DM
DM6
DQS
DQS6
D7
/CS
DM
DM7
DQS
DQS7
D4
DM
DQS
DQS4
/RCS0
Notes:
1. DQ-to-I/O wiring may be changed within a byte
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ/DQS resistors should be 22 Ohms.
4. VDDID strap connections(for memory device VDD, VDDQ);
Strap out :(open) : VDD=VDDQ
Strap In (Vss) : VDD=VDDQ
5. SDRAM placement alternates btw the back and
front sides for the DIMM
6. Address and control resistors should be 22 Ohms
SCL
Serial PD
A0
A1
A2
SA0
SA1
SA2
WP
SDA
/CS
DM
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
D8
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS8
/RCS0 -->/S0 : SDRAMs D0-D8
RBA0-RBA1 -->BA0-BA1 : SDRAMs D0 - D8
RA0 -R A11 -->A0 - A11 : SDRAMs D0 - D8
/RRAS --> /RAS : SDRAMs D0 - D8
/RCAS --> /CAS : SDRAMs D0 - D8
RCKE0 --> CKE : SDRAMs D0 - D8
/RWE --> /WE : SDRAMs D0 - D8
/CS0
BA0-BA1
A0-A11
/RAS
/CAS
CKE0
/WE
R
E
G
PCK
/PCK
/RESET
CK0, /CK0 --------- PLL*
* Wire per clock loading table/wiring diagrams
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
.
VDDSPD
VREF
VSS
VDDID
D0 - D8
D0 - D8
D0 - D8
D0 - D8
=
.
=
.
.
=
.
.
.
..
Strap:see Note 4
VDD
SPD
VDDQ
=
.
.
D0
/CS
DM
DM0
DQS
DQS0
D1
/CS
DM
DM1
DQS
DQS1
D2
/CS
DM
DM2
DQS
DQS2
/CS
DM
DM3
D3
DQS
DQS3
D4
CS
DM
DM4
DQS
D5
/CS
DM
DM5
DQS
DQS5
D6
/CS
DM
DM6
DQS
DQS6
D7
/CS
DM
DM7
DQS
DQS7
D4
DM
DQS
DQS4
/RCS0
Notes:
1. DQ-to-I/O wiring may be changed within a byte
2. DQ/DQS/DM/CKE/CS relationships must be
maintained as shown.
3. DQ/DQS resistors should be 22 Ohms.
4. VDDID strap connections(for memory device VDD, VDDQ);
Strap out :(open) : VDD=VDDQ
Strap In (Vss) : VDD=VDDQ
5. SDRAM placement alternates btw the back and
front sides for the DIMM
6. Address and control resistors should be 22 Ohms
SCL
Serial PD
A0
A1
A2
SA0
SA1
SA2
WP
SDA
/CS
DM
DM8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
D8
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS
DQS8
/RCS0 -->/S0 : SDRAMs D0-D8
RBA0-RBA1 -->BA0-BA1 : SDRAMs D0 - D8
RA0 -R A11 -->A0 - A11 : SDRAMs D0 - D8
/RRAS --> /RAS : SDRAMs D0 - D8
/RCAS --> /CAS : SDRAMs D0 - D8
RCKE0 --> CKE : SDRAMs D0 - D8
/RWE --> /WE : SDRAMs D0 - D8
/CS0
BA0-BA1
A0-A11
/RAS
/CAS
CKE0
/WE
R
E
G
PCK
/PCK
/RESET
CK0, /CK0 --------- PLL*
* Wire per clock loading table/wiring diagrams
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
.
VDDSPD
VREF
VSS
VDDID
D0 - D8
D0 - D8
D0 - D8
D0 - D8
=
.
=
.
.
=
.
.
.
..
Strap:see Note 4
VDD
SPD
VDDQ
=
.
.
HYMD116G725A(L)8-K/H/L
Rev. 0.5/May. 02 4
ABSOLUTE MAXIMUM RATINGS
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to V
SS
=0V)
Note :
1. V
DDQ
must not exceed the level of V
DD
.
2. V
IL
(min) is acceptable -1.5V AC pulse width with < 5ns of duration.
3. The value of V
REF
is approximately equal to 0.5V
DDQ
.
AC OPERATING CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to V
SS
=0V)
Note :
1. VID is the magnitude of the difference between the input level on CK and the input on /CK.
2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
Parameter
Symbol
Rating
Unit
Ambient Temperature
T
A
0 ~ 70
o
C
Storage Temperature
T
STG
-55 ~ 125
o
C
Voltage on Any Pin relative to V
SS
V
IN
, V
OUT
-0.5 ~ 3.6
V
Voltage on V
DD
relative to V
SS
V
DD
-0.5 ~ 3.6
V
Voltage on V
DDQ
relative to V
SS
V
DDQ
-0.5 ~ 3.6
V
Output Short Circuit Current
I
OS
50
mA
Power Dissipation
P
D
9
W
Soldering Temperature / Time
T
SOLDER
260 / 10
o
C / Sec
Parameter
Symbol
Min
Typ.
Max
Unit
Note
Power Supply Voltage
V
DD
2.3
2.5
2.7
V
Power Supply Voltage
V
DDQ
2.3
2.5
2.7
V
1
Input High Voltage
V
IH
V
REF
+ 0.15
-
V
DDQ
+ 0.3
V
Input Low Voltage
V
IL
-0.3
-
V
REF
- 0.15
V
2
Termination Voltage
V
TT
V
REF
- 0.04
V
REF
V
REF
+ 0.04
V
Reference Voltage
V
REF
0.49*VDDQ
0.5*VDDQ
0.51*VDDQ
V
3
Parameter
Symbol
Min
Max
Unit
Note
Input High (Logic 1) Voltage, DQ, DQS and DM sig-
nals
V
IH(AC)
V
REF
+ 0.31
V
Input Low (Logic 0) Voltage, DQ, DQS and DM signals
V
IL(AC)
V
REF
- 0.31
V
Input Differential Voltage, CK and /CK inputs
V
ID(AC)
0.7
V
DDQ
+ 0.6
V
1
Input Crossing Point Voltage, CK and /CK inputs
V
IX(AC)
0.5*V
DDQ
-0.2
0.5*V
DDQ
+0.2
V
2
HYMD116G725A(L)8-K/H/L
Rev. 0.5/May. 02 5
AC OPERATING TEST CONDITIONS
(TA=0 to 70
o
C, Voltage referenced to VSS=0V)
Parameter
Value
Unit
Reference Voltage
V
DDQ
x 0.5
V
Termination Voltage
V
DDQ
x 0.5
V
AC Input High Level Voltage (V
IH
, min)
V
REF
+ 0.31
V
AC Input Low Level Voltage (V
IL
, max)
V
REF
- 0.31
V
Input Timing Measurement Reference Level Voltage
V
REF
V
Output Timing Measurement Reference Level Voltage
V
TT
V
Input Signal maximum peak swing
1.5
V
Input minimum Signal Slew Rate
1
V/ns
Termination Resistor (R
T
)
50
W
Series Resistor (R
S
)
25
W
Output Load Capacitance for Access Time Measurement (C
L
)
30
pF
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