MK3727
MDS 3727 E
1
Revision 032603
I n t e g r a t e d C i r cu i t S y st e m s
q
5 2 5 Ra ce S t r e e t , S a n J o s e , C A 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. i c s t . c o m
L
OW
C
OST
24 - 36 MH
Z
3.3 V
OLT
VCXO
Description
The MK3727 series of devices include the original
MK3727S, MK3727A, and the new MK3727C and
MK3727D. The MK3727D and MK3727C are drop-in
replacements for the MK3727S and MK3727A devices.
Compared to these earlier devices the MK3727D and
MK3727C offer a wider operating frequency range and
improved power supply noise rejection. The MK3727D
is recommended for new designs.
The MK3727 series combines the functions of a VCXO
(Voltage Controlled Crystal Oscillator) and PLL (Phase
Locked Loop) frequency doubler onto a single chip.
Used in conjunction with an external pullable quartz
crystal, this monolithic integrated circuit replaces more
costly hybrid (canned) VCXO devices. The MK3727 is
designed primarily for data and clock recovery
applications within end products such as ADSL
modems, set-top box receivers, and telecom systems.
The MK3727D is recommended for new designs. The
MK3727D exhibits a moderate VCXO gain of
120ppm/V typical, when used with a high quality
external pullable quartz crystal. The MK3727C offers a
higher VCXO gain of 150ppm/V, similar to the earlier
MK3727A. The higher intrinsic VCXO gain of the
MK3727C may help compensate for the reduced
pullability of a low quality crystal used in some
applications. However, higher VCXO gain may also
increase clock output phase noise.
The frequency of the on-chip VCXO is adjusted by an
external control voltage input into pin VIN. Because
VIN is a high impedance input, it can be driven directly
from an PWM RC integrator circuit. Frequency output
increases with VIN voltage input. The usable range of
VIN is 0 to 3V.
Features
MK3727D and MK3727C are drop-in upgrades to the
earlier MK3727S and MK3727A devices
MK3727D and MK3727C offer 24-36 MHz output
frequency range (output frequency = 2x crystal
frequency) and improved power supply noise
rejection
Uses an inexpensive 12 to 18 MHz external crystal
Ideal for ADSL applications using 17.664 MHz
external pullable crystal to generate locked 35.328
MHz clock physical layer clock
Ideal for set-top box applications using 13.5 MHz
external pullable crystal to generate lock 27 MHz
clock transport video clock
On-chip VCXO with guaranteed pull range of 115
ppm minimum (MK3727D)
VCXO input tuning voltage 0 to 3.3 V
Packaged in 8 pin SOIC (150 mil wide)
MK3727D is Recommended for New Designs.
Block Diagram
2 4-36 M H z
(2 x C rystal F requ enc y)
X 1
X 2
V o ltag e
C o n tro lle d
C rysta l
O sc illato r
P L L
Freq u en cy
D o ub ler
V IN
1 2-1 8 M H z
P ullable
C ry sta l
L
OW
C
OST
24 - 36 MH
Z
3.3 V
OLT
VCXO
MDS 3727 E
2
Revision 032603
I n t e g r a t e d C i r c u i t S y s t e ms
q
5 2 5 R a c e S t r e e t , S a n J o s e , CA 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
MK3727
Pin Assignment
Pin Descriptions
X 1
V D D
V I N
G N D
G N D
N C
C L K
X 2
1
2
3
4
8
7
6
5
M K 3 7 2 7 S
M K 3 7 2 7 A
M K 3 7 2 7 C
M K 3 7 2 7 D
8 P i n ( 1 5 0 m i l ) S O I C
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
XI
Input
Crystal connection -- Connect to the external pullable crystal.
2
VDD
Power
Connect to +3.3 V (0.01uf decoupling capacitor recommended)
3
VIN
Input
Voltage input to VCXO -- 0 to 3.3 V analog input which controls the
oscillation frequency of the VCXO.
4
GND
Power
Connect to ground
5
CLK
Output
Clock output
6
NC
--
No internal connection (may connect to ground or VDD)
7
GND
Power
Connect to ground
8
X2
Input
Crystal connection -- Connect to the external pullable crystal.
L
OW
C
OST
24 - 36 MH
Z
3.3 V
OLT
VCXO
MDS 3727 E
3
Revision 032603
I n t e g r a t e d C i r c u i t S y s t e ms
q
5 2 5 R a c e S t r e e t , S a n J o s e , CA 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
MK3727
External Component Selection
The MK3727 requires a minimum number of external
components for proper operation.
Decoupling Capacitor
A decoupling capacitor of 0.01F must be connected
between VDD (pin 2) and GND (pin 4), as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
When the PCB trace between the clock output (CLK,
pin 5) and the load is over 1 inch, series termination
should be used. To series terminate a 50
trace (a
commonly used trace impedance) place a 33
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
.
Quartz Crystal
The MK3727 VCXO function consists of the external
crystal and the integrated VCXO oscillator circuit. To
assure the best system performance (frequency pull
range) and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the
following section shown must be followed.
The frequency of oscillation of a quartz crystal is
determined by its "cut" and by the load capacitors
connected to it. The MK3727 incorporates on-chip
variable load capacitors that "pull" (change) the
frequency of the crystal. The crystal specified for use
with the MK3727 is designed to have zero frequency
error when the total of on-chip + stray capacitance is
14pF.
Recommended Crystal Parameters:
Initial Accuracy at 25
C
20 ppm
Temperature Stability
30 ppm
Aging
20 ppm
Load Capacitance
14 pf
Shunt Capacitance, C0
7 pF Max
C0/C1 Ratio
250 Max
Equivalent Series Resistance
35
Max
The external crystal must be connected as close to the
chip as possible and should be on the same side of the
PCB as the MK3727. There should be no via's between
the crystal pins and the X1 and X2 device pins. There
should be no signal traces underneath or close to the
crystal.
Crystal Tuning Load Capacitors
The crystal traces should include pads for small fixed
capacitors, one between X1 and ground, and another
between X2 and ground. Stuffing of these capacitors
on the PCB is optional. The need for these capacitors
is determined at system prototype evaluation, and is
influenced by the particular crystal used (manufacture
and frequency) and by PCB layout. The typical required
capacitor value is 1 to 4 pF.
To determine the need for and value of the crystal
adjustment capacitors, you will need a PC board of
your final layout, a frequency counter capable of about
1 ppm resolution and accuracy, two power supplies,
and some samples of the crystals which you plan to
use in production, along with measured initial accuracy
for each crystal at the specified crystal load
capacitance, CL.
To determine the value of the crystal capacitors:
1. Connect VDD of the MK3727 to 3.3V. Connect pin 3
of the MK3727 to the second power supply. Adjust the
voltage on pin 3 to 0V. Measure and record the
frequency of the CLK output.
2. Adjust the voltage on pin 3 to 3.3V. Measure and
record the frequency of the same output.
To calculate the centering error:
Where:
f
target
= nominal crystal frequency
error
xtal
=actual initial accuracy (in ppm) of the crystal
being measured
If the centering error is less than 25 ppm, no
adjustment is needed. If the centering error is more
than 25ppm negative, the PC board has excessive
stray capacitance and a new PCB layout should be
Error
10
6
x
f
3.0V
f
t
et
arg
(
)
f
0V
f
t
et
arg
(
)
+
f
t
et
arg
------------------------------------------------------------------------------
error
xtal
=
L
OW
C
OST
24 - 36 MH
Z
3.3 V
OLT
VCXO
MDS 3727 E
4
Revision 032603
I n t e g r a t e d C i r c u i t S y s t e ms
q
5 2 5 R a c e S t r e e t , S a n J o s e , CA 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
MK3727
considered to reduce stray capacitance. (Alternately,
the crystal may be re-specified to a higher load
capacitance. Contact ICS MicroClock for details.) If the
centering error is more than 25ppm positive, add
identical fixed centering capacitors from each crystal
pin to ground. The value for each of these caps (in pF)
is given by:
External Capacitor =
2 x (centering error)/(trim sensitivity)
Trim sensitivity is a parameter which can be supplied
by your crystal vendor. If you do not know the value,
assume it is 30 ppm/pF. After any changes, repeat the
measurement to verify that the remaining error is
acceptably low (typically less than 25ppm).
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK3727. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Recommended Operation Conditions
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5V to VDD+0.5V
Ambient Operating Temperature
0 to +70
C
Storage Temperature
-65 to +150
C
Soldering Temperature
260
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
0
+70
C
Power Supply Voltage (measured in respect to GND)
+3.15
+3.45
V
Reference crystal parameters
Refer to page 3
L
OW
C
OST
24 - 36 MH
Z
3.3 V
OLT
VCXO
MDS 3727 E
5
Revision 032603
I n t e g r a t e d C i r c u i t S y s t e ms
q
5 2 5 R a c e S t r e e t , S a n J o s e , CA 9 5 1 2 6
q
t e l ( 4 0 8 ) 2 9 5 - 9 8 0 0
q
w w w. ic s t . c o m
MK3727
DC Electrical Characteristics
VDD=3.3V 5%
, Ambient temperature 0 to +70
C, unless stated otherwise
AC Electrical Characteristics
VDD = 3.3V 5%
, Ambient Temperature 0 to +70
C, unless stated otherwise
Note 1: External crystal device must conform with Pullable Crystal Specifications listed on page 3.
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.15
3.45
V
Output High Voltage
V
OH
I
OH
= -12 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 12 mA
0.4
V
Output High Voltage (CMOS
Level)
V
OH
I
OH
= -4 mA
VDD-0.4
V
Operating Supply Current
IDD
Output = 27 MHz,
no load
10
mA
Short Circuit Current
I
OS
50
mA
VIN, VCXO Control Voltage
V
IA
0
3.3
V
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Output Frequency
MK3727D and
MK3727C
F
O
VCXO Crystal frequency =
1/2 Output
24
36
MHz
MK3727A and
MK3727S
F
O
VCXO Crystal frequency =
13.5 MHz
27
MHz
Crystal Pullability
MK3727D and
MK3727C
F
P
0V< VIN < 3.3V, Note 1
+ 115
ppm
MK3727A and
MK3727S
F
P
0V< VIN < 3.3V, Note 1
+ 100
ppm
VCXO Gain
MK3727D
VIN = VDD/2 + 1V, Note 1
120
ppm/V
MK3727C
VIN = VDD/2 + 1V, Note 1
150
ppm/V
MK3727A
VIN = VDD/2 + 1V, Note 1
170
ppm/V
MK3727S
VIN = VDD/2 + 1V, Note 1
100
ppm/V
Output Rise Time
t
OR
0.8 to 2.0V, C
L
=15pF
1.5
ns
Output Fall Time
t
OF
2.0 to 0.8V, C
L
=15pF
1.5
ns
Output Clock Duty Cycle
t
D
Measured at 1.4V, C
L
=15pF
40
50
60
%
Maximum Output Jitter,
short term
t
J
C
L
=15pF
100
ps
PDF 
ZIP