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8745AY
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 12, 2003
1
Integrated
Circuit
Systems, Inc.
ICS8745
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS8745 is a highly versatile 1:5 LVDS Clock
Generator and a member of the HiPerClockSTM
family of High Performance Clock Solutions from
ICS. The ICS8745 has a fully integrated PLL and
can be configured as zero delay buffer, multi-
plier or divider, and has an output frequency range of
31.25MHz to 700MHz. The Reference Divider, Feedback Di-
vider and Output Divider are each programmable, thereby
allowing for the following output-to-input frequency ratios:
8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows
the device to achieve "zero delay" between the input clock
and the output clocks. The PLL_SEL pin can be used to
bypass the PLL for system test and debug purposes. In
bypass mode, the reference clock is routed around the PLL
and into the internal output dividers.
F
EATURES
5 differential LVDS outputs designed to meet
or exceed the requirements of ANSI TIA/EIA-644
Selectable differential clock inputs
CLKx, nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
Output frequency range: 31.25MHz to 700MHz
Input frequency range: 31.25MHz to 700MHz
VCO range: 250MHz to 700MHz
External feedback for "zero delay" clock regeneration
with configurable frequencies
Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
Cycle-to-cycle jitter: 25ps (maximum)
Output skew: 35ps (maximum)
Static phase offset: 50ps 150ps
3.3V supply voltage
0C to 70C ambient operating temperature
Industrial temperature information available upon request
HiPerClockSTM
,&6
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q3
nQ3
V
DDO
Q2
nQ2
GND
Q1
nQ1
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
V
DDO
Q0
nQ0
GND
SEL2
FB_IN
nFB_IN
V
DD
GND
nQ4
Q4
V
DDO
SEL3
V
DDA
PLL_SEL
V
DD
ICS8745
PLL_SEL
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
FB_IN
nFB_IN
SEL0
SEL1
SEL2
SEL3
MR
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
0
1
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
0
1
1, 2, 4, 8,
16, 32
,
64
8745AY
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 12, 2003
2
Integrated
Circuit
Systems, Inc.
ICS8745
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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8745AY
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 12, 2003
3
Integrated
Circuit
Systems, Inc.
ICS8745
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
3A. C
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_
L
L
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s
s
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p
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L
L
P
3
L
E
S
2
L
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1
L
E
S
0
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S
4
Q
n
:
0
Q
n
,
4
Q
:
0
Q
0
0
0
0
4
0
0
0
1
4
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1
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4
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8
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1
8745AY
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 12, 2003
4
Integrated
Circuit
Systems, Inc.
ICS8745
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
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t
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m
a
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P
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3
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3
5
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5
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3
.
3
5
6
4
.
3
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V
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D
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y
l
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5
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3
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3
5
6
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.
3
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I
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t
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p
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w
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P
0
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m
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D
t
n
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p
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g
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5
1
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m
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D
t
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C
y
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p
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t
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p
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0
2
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m
l
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b
m
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r
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m
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3
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L
C
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D
V
=
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V
5
6
4
.
3
=
5
A
I
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p
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w
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F
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1
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L
C
,
0
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L
C
V
D
D
V
,
V
5
6
4
.
3
=
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0
=
5
-
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1
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L
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V
,
V
5
6
4
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3
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V
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0
+
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D
5
8
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T
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D
.
V
3
.
0
+
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
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h
g
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t
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p
n
I
2
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D
D
3
.
0
+
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V
L
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a
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w
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I
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D
D
V
=
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5
6
4
.
3
=
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1
A
L
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S
_
L
L
P
V
D
D
V
=
N
I
V
5
6
4
.
3
=
5
A
I
L
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t
n
e
r
r
u
C
w
o
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t
u
p
n
I
,
0
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E
S
,
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M
,
L
E
S
_
K
L
C
3
L
E
S
,
2
L
E
S
,
1
L
E
S
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
5
-
A
L
E
S
_
L
L
P
V
D
D
V
,
V
5
6
4
.
3
=
N
I
V
0
=
0
5
1
-
A
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
8745AY
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 12, 2003
5
Integrated
Circuit
Systems, Inc.
ICS8745
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
4D. LVDS DC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
n
o
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t
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d
n
o
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t
s
e
T
m
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m
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n
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M
l
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c
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p
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1
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2
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3
.
1
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a
M
5
5
2
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m
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3
-
A
m
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e
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t
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p
t
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5
.
3
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A
m
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g
a
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f
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w
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P
0
2
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1
0
2
+
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V
H
O
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g
i
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g
a
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t
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p
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4
3
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1
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e
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a
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t
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p
t
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9
.
0
6
0
.
1
V
T
ABLE
5. I
NPUT
F
REQUENCY
C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
l
o
b
m
y
S
r
e
t
e
m
a
r
a
P
s
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m
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c
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q
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t
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p
n
I
,
0
K
L
C
n
,
0
K
L
C
1
K
L
C
n
,
1
K
L
C
1
=
L
E
S
_
L
L
P
5
2
.
1
3
0
0
7
z
H
M
0
=
L
E
S
_
L
L
P
0
0
7
z
H
M
T
ABLE
6. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V5%, T
A
= 0C
TO
70C
l
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b
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1
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;
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8745AY
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REV. D FEBRUARY 12, 2003
6
Integrated
Circuit
Systems, Inc.
ICS8745
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
P
ARAMETER
M
EASUREMENT
I
NFORMATION
D
IFFERENTIAL
I
NPUT
L
EVEL
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVDS
3.3V5%
POWER SUPPLY
+
-
Float GND
3.3V
P
HASE
J
ITTER
AND
S
TATIC
P
HASE
O
FFSET
V
CMR
Cross Points
V
PP
GND
CLK0,
CLK1
nCLK0,
nCLK1
V
DD
P
ROPAGATION
D
ELAY
O
UTPUT
R
ISE
/F
ALL
T
IME
Clock Outputs
20%
80%
20%
80%
t
R
t
F
V
O D
tsk(o)
Qx
Qy
O
UTPUT
S
KEW
t
PD
nQx
nQy
Q0:Q4
nQ0:nQ4
(where
t() is any random sample, and t()
mean
is the average
of the sampled cycles measured on controlled edges)
t ()
mean
= Static Phase Offset
t()
V
OH
V
OL
V
OH
V
OL
nFB_IN
FB_IN
tjit() = t() -- t()
mean
= Phase Jitter
CLK0,
CLK1
nCLK0,
nCLK1
CLK0,
CLK1
nCLK0,
nCLK1
8745AY
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REV. D FEBRUARY 12, 2003
7
Integrated
Circuit
Systems, Inc.
ICS8745
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
Pulse Width
t
PERIOD
V
OS
S
ETUP
t
PW
& t
P
ERIOD
V
OD
S
ETUP
I
OS
S
ETUP
I
OFF
S
ETUP
I
OSD
S
ETUP
Q0:Q4
nQ0:nQ4
out
out
LVDS
DC Input
V
OS
/
V
OS
V
DD
100
out
out
LVDS
DC Input
V
OD
/
V
OD
V
DD
out
out
LVDS
DC Input
I
OSD
V
DD
out
LVDS
DC Input
I
OS
I
OSB
V
DD
out
LVDS
I
OFF
V
DD
8745AY
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REV. D FEBRUARY 12, 2003
8
Integrated
Circuit
Systems, Inc.
ICS8745
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
A
PPLICATION
I
NFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8745 provides sepa-
r a t e p o w e r s u p p l i e s t o i s o l a t e a n y h i g h s w i t c h i n g
noise from the outputs to the internal PLL. V
DD
, V
DDA
, and V
DDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required.
Figure 2 illustrates how
a 10
resistor along with a 10
F and a .01
F bypass
capacitor should be connected to each V
DDA
pin.
P
OWER
S
UPPLY
F
ILTERING
T
ECHNIQUES
F
IGURE
2. P
OWER
S
UPPLY
F
ILTERING
10
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLKx
nCLKx
VDD
8745AY
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REV. D FEBRUARY 12, 2003
9
Integrated
Circuit
Systems, Inc.
ICS8745
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
F
IGURE
3A. ICS8745 LVDS Z
ERO
D
ELAY
B
UFFER
S
CHEMATIC
E
XAMPLE
L
AYOUT
G
UIDELINE
The schematic of the ICS8745 layout example is shown in
Figure 3A. The ICS8745 recommended PCB board layout for
this example is shown in
Figure 3B. This layout example is
used as a general guideline. The layout in the actual system
U3
8745
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
VD
D
nFB
_
I
N
FB_I
N
SEL
2
GND
nQ
0
Q0
V
DDO
nQ1
Q1
GND
nQ2
Q2
VDDO
nQ3
Q3
VD
D
PL
L
_
SEL
V
DDA
SEL
3
V
DDO
Q4
nQ
4
GND
SP = Space (i.e. not intstalled)
C16
10u
CLK_SEL
C2
0.1uF
VDDO=3.3V
C11
0.01u
RD3
SP
VDD
(U1-9)
VDD=3.3V
SEL[3:0] = 0101,
Divide by 2
RU3
1K
Zo = 50 Ohm
(77.76 MHz)
RU4
1K
RU5
SP
SEL0
RD4
SP
(155.5 MHz)
SEL2
RU6
1K
C4
0.1uF
C1
0.1uF
RU7
SP
3.3V PECL Driver
CLK_SEL
RD2
1K
RD5
1K
VDDO
SEL1
VDDO
(U1-28)
SEL
3
R8A
50
R7
10
R9
50
Zo = 50 Ohm
R2
100
Decoupling capacitor located near the power pins
R10
50
SEL3
RU2
SP
RD6
SP
R4
100
VDD
SEL0
(U1-32)
SEL2
C6
0.1uF
RD7
1K
Zo = 50 Ohm
SEL1
3.3V
(U1-16)
PLL_SEL
VDD
VDD
VDDA
(U1-22)
C5
0.1uF
PL
L
_
SEL
Zo = 50 Ohm
LVDS_input
+
-
will depend on the selected component types, the density of
the components, the density of the traces, and the stack up
of the P.C. board.
8745AY
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REV. D FEBRUARY 12, 2003
10
Integrated
Circuit
Systems, Inc.
ICS8745
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
F
IGURE
3B. PCB B
OARD
L
AYOUT
F
OR
ICS8745
The following component footprints are used in this layout
example:
All the resistors and capacitors are size 0603.
P
OWER
AND
G
ROUNDING
Place the decoupling capacitors C1, C6, C2, C4, and C5, as
close as possible to the power pins. If space allows, placement
of the decoupling capacitor on the component side is preferred.
This can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the V
DDA
pin as possible.
C
LOCK
T
RACES
AND
T
ERMINATION
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
The differential 50
output traces should have same
length.
Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Make sure no other signal traces are routed between the
clock trace pair.
The matching termination resistors should be located as
close to the receiver input pins as possible.
C16
GND
U1
C5
50 Ohm
Traces
C2
VDDA
VDDO
VIA
Pin 1
C4
R7
C11
VDD
C6
C1
8745AY
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REV. D FEBRUARY 12, 2003
11
Integrated
Circuit
Systems, Inc.
ICS8745
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
RANSISTOR
C
OUNT
The transistor count for ICS8745 is: 3050
T
ABLE
7.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8C/W
55.9C/W
50.1C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9C/W
42.1C/W
39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
R
ELIABILITY
I
NFORMATION
8745AY
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REV. D FEBRUARY 12, 2003
12
Integrated
Circuit
Systems, Inc.
ICS8745
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
P
ACKAGE
O
UTLINE
- Y S
UFFIX
T
ABLE
8. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-026
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8745AY
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REV. D FEBRUARY 12, 2003
13
Integrated
Circuit
Systems, Inc.
ICS8745
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
ABLE
9. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
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8745AY
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 12, 2003
14
Integrated
Circuit
Systems, Inc.
ICS8745
1:5 D
IFFERENTIAL
-
TO
-LVDS
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
T
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