Integrated
Circuit
Systems, Inc.
General Description
Features
AV9110
Block Diagram
Serially Programmable Frequency Generator
9110 Rev F 5/30/00
Complete user programmability of output frequency
through serial input data port
On-chip Phase-Locked Loop for clock generation
Generates accurate frequencies up to 130 MHz
Tristate CMOS outputs
5 volt power supply
Low power CMOS technology
14-pin DIP or 150-mil SOIC
Very low jitter
Wide operating range VCO
The AV9110 generates user specified clock frequencies using
an externally generated input reference, such as 14.318 MHz
or 10.00 MHz crystal connected between pins 1 and 14.
Alternately, a TTL input reference clock signal can be used.
The output frequency is determined by a 24-bit digital word
entered through the serial port. The serial port enables the
user to change the output frequency on-the-fly.
The clock outputs utilize CMOS level output buffers that
operate up to 130 MHz.
Applications
Graphics: The AV9110 generates low jitter, high speed pixel
(or dot) clocks. It can be used to replace multiple expensive
high speed crystal oscillators. The flexibility of this device
allows it to generate nonstandard graphics clocks, allowing
the user to program frequencies on-the-fly.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
2
AV9110
Pin Descriptions
Pin Configuration
14 Pin Dip, SOIC
The AV9110 requires a stable reference clock (5 to 32 MHz) to
generate a stable, low jitter output clock. The AV9 11 0 -01 is
optimized to use an external quartz crystal as a frequency
reference, without the need of additional external components.
The AV9110-02 is optimized to accept an TTL clock
reference. Either device can be used with an external crystal
or accept a TTL clock reference, although extra components
may be required. The various combinations implied are
summarized in Figure 2 (see page 7).
Clock Reference Implementations:
AV9110-01 vs. AV9110-02
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3
AV9110
Electrical Characteristics
V
DD
= +5V10%, T
A
= 0 70
C unless otherwise stated
Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Voltage on I/O pins referenced to GND . . . . . . GND 0.5 V to V
DD
+0.5 V
Operating Temperature under bias . . . . . . . . . . 0C to +70C
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . 0.8 Watts
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
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4
AV9110
Serial Programming
The AV9110 is programmed to generate clock frequencies by
entering data through the shift register. Figure 1 displays the
proper timing sequence. On the negative going edge of CE#,
the shift register is enabled and the data at the DATA pin is
loaded into the shift register on the rising edge of the SCLK.
Bit D0 is loaded first, followed by D1, D2, etc. This data
consists of the 24 bits shown in the Shift Register Bit
Assignment in Table 1, and therefore takes 24 clock cycles to
load. An internal counter then disables the input and transfers
the data to internal latches on the rising edge of the 24th
cycle of the SCLK. Any data entered after the 24th cycle is
ignored until CE# must remain low for a minimum of 24 SLCK
clock cycles. If CE# is taken high before 24 clock cycles have
elapsed, the data is ignored (no frequency change occurs)
and the counter is reset. Tables 1 and 2 display the bit location
for generating the output clock frequency and the output
divider circuitry, respectively.
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5
AV9110
Output Divider Turth Tables
1
D
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4
1
1
8
Table 2
1
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8
Table 3
Programming the PLL
The AV9110 has a wide operating range but it is recommended that it is operated within the following limits:
The AV9110 is a classical PLL circuit and the VCO output frequency is given by:
f
VCO
=
NV fREF
M
Where N = VCO divided, 3 to 127
M =m Reference divide, 3 to 127
V = Perscale, 1 or 8
The 2 output drivers then give the following frequencies:
f
CLK
=
f
VCO
R
=
NV fREF
MR
or f
REF
(output mixable by bit 17)
f
CLK/X
=
=
f
VCLK
X
Where R, X = output dividers 1, 2, 4 or 8
f
VCO
RX
Notes:
1. Output frequency accuracy will depend solely on input reference frequency accuracy.
2. For output frequencies below 125 MHz, it is recommended that the VCO output divide, R, should be 2 or greater. This will
give improved duty cycle.
3. The minimum output frequency step size is approximately 0.2% due to the divider range provided.
f
<
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REF
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