Document Outline
- General Description
- Features
- Block Diagram
- Pin Assignment
- Pin Descriptions
- Pin Characteristics
- Clock Select Function Table
- Clock Input Function Table
- Absolute Maximum Ratings
- Power Supply 3.3V DC Characteristics
- Power Supply 3.3V/2.5V DC Characteristics
- Power Supply 2.5V DC Characteristics
- 3.3V DC Characteristics
- 3.3V/2.5V DC Characteristics
- 2.5V DC Characteristics
- 3.3V AC Characteristics
- 3.3V/2.5V AC Characteristics
- 2.5V AC Characteristics
- Parameter Measurement Information
- Application Information
- Wiring the Differential Input to Accept Single Ended Levels
- Recommendations for Unused Input and Output Pins
- Differential Clock Input Interface
- Schematic Example
- Reliability Information
- Transistor Count
- Package Outline
- Package Dimensions
- Ordering Information
- Revision History Sheet
8308AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
1
Integrated
Circuit
Systems, Inc.
ICS8308I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
/LVCMOS-
TO
-LVCMOS F
ANOUT
B
UFFER
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS8308I
24-Lead, 300-MIL TSSOP
4.4mm x 7.8mm x 0.92mm body package
G Package
Top View
Q0
GND
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
V
DD
GND
Q1
V
DDO
V
DDO
Q2
GND
Q3
V
DDO
Q4
GND
Q5
V
DDO
Q6
GND
Q7
G
ENERAL
D
ESCRIPTION
The ICS8308I is a low-skew, 1-to-8 Fanout Buffer
and a member of the HiPerClockS
TM
family of
High Performance Clock Solutions from ICS. The
ICS8308I has two selectable clock inputs. The
CLK, nCLK pair can accept most differential input
levels. The LVCMOS_CLK can accept LVCMOS or LVTTL
input levels. The low impedance LVCMOS/LVTTL outputs
are designed to drive 50
series or parallel terminated
transmission lines. The effective fanout can be increased
from 8 to 16 by utilizing the ability of the outputs to drive two
series terminated transmission lines.
The ICS8308I is characterized for 3.3V core/3.3V output,
3.3V core/2.5V output or 2.5V core/2.5V output operation.
Guaranteed output and part-part skew characteristics make
the 8308I ideal for those clock distribution applications requiring
well defined performance and repeatability.
F
EATURES
8 LVCMOS/LVTTL outputs (7
typical output impedance)
Selectable LVCMOS_CLK or differential CLK, nCLK
inputs
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum Output Frequency: 350MHz
Output Skew: (3.3V 5%): 100ps (maximum)
Part to Part Skew: (3.3V 5%): 1ns (maximum)
Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
-40
C to 85
C ambient operating temperature
Available in both, Standard and RoHS/Lead-Free
compliant packages
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
LVCMOS_CLK
CLK
nCLK
CLK_SEL
CLK_EN
OE
D
LE
Q
1
0
Pullup
Pullup
Pullup
Pulldown
Pullup
Pullup
8308AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
2
Integrated
Circuit
Systems, Inc.
ICS8308I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
/LVCMOS-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
1. P
IN
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8308AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
3
Integrated
Circuit
Systems, Inc.
ICS8308I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
/LVCMOS-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DDO
= 3.3V5%, T
A
= -40
TO
85
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDO
+ 0.5V
Package Thermal Impedance,
JA
70C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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8308AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
4
Integrated
Circuit
Systems, Inc.
ICS8308I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
/LVCMOS-
TO
-LVCMOS F
ANOUT
B
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T
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4D. DC C
HARACTERISTICS
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8308AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
5
Integrated
Circuit
Systems, Inc.
ICS8308I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
/LVCMOS-
TO
-LVCMOS F
ANOUT
B
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T
ABLE
4F. DC C
HARACTERISTICS
,
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8308AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
6
Integrated
Circuit
Systems, Inc.
ICS8308I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
/LVCMOS-
TO
-LVCMOS F
ANOUT
B
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T
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5B. AC C
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7
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8308AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
7
Integrated
Circuit
Systems, Inc.
ICS8308I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
/LVCMOS-
TO
-LVCMOS F
ANOUT
B
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T
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5C. AC C
HARACTERISTICS
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a
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t
d
l
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H
d
n
a
p
u
t
e
S
:
6
E
T
O
N
.
5
6
d
r
a
d
n
a
t
S
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E
D
E
J
h
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T
O
N
8308AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
8
Integrated
Circuit
Systems, Inc.
ICS8308I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
/LVCMOS-
TO
-LVCMOS F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
V
CMR
Cross Points
V
PP
nCLK
CLK
GND
V
DD
Qx
Qy
tsk(o)
V
DDO
2
V
DDO
2
Qx
Qy
PART 1
PART 2
tsk(pp)
V
DDO
2
V
DDO
2
2.5V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/2.5V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
3.3V C
ORE
/3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
1.65V5%
-1.65V5%
D
IFFERENTIAL
I
NPUT
L
EVEL
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
SCOPE
Qx
LVCMOS
V
DDO
2
2.05V5%
-1.25V5%
GND
V
DD
,
V
DDO
GND
V
DD
SCOPE
Qx
LVCMOS
1.25V5%
-1.25V5%
GND
V
DD
,
V
DDO
V
DDO
1.25V5%
8308AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
9
Integrated
Circuit
Systems, Inc.
ICS8308I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
/LVCMOS-
TO
-LVCMOS F
ANOUT
B
UFFER
O
UTPUT
R
ISE
/F
ALL
T
IME
P
ROPAGATION
D
ELAY
nCLK
CLK
Q0:Q7
t
PD
V
DDO
2
V
DDO
2
LVCMOS_
CLK
Clock
Outputs
0.8V
2V
2V
0.8V
t
R
t
F
Clock
Outputs
0.6V
1.8V
1.8V
0.6V
t
R
t
F
V
DD
=
V
DDO
= 3.3V
V
DD
=
V
DDO
= 2.5V or
V
DD
=
3.3V, V
DDO
= 2.5V
O
UTPUT
D
UTY
C
YCLE
/P
ULSE
W
IDTH
/P
ERIOD
Q0:Q7
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
t
PW
8308AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
10
Integrated
Circuit
Systems, Inc.
ICS8308I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
/LVCMOS-
TO
-LVCMOS F
ANOUT
B
UFFER
A
PPLICATION
I
NFORMATION
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
F
IGURE
1. S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
I
NPUTS
:
CLK I
NPUT
:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1k
resistor can be tied from the CLK input to
ground.
CLK/nCLK I
NPUT
:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1k
resistor can be tied from
CLK to ground.
S
ELECT
P
INS
:
All select pins have internal pull-ups and pull-downs;
additional resistance is not required but can be added for
additional protection. A 1k
resistor can be used.
R
ECOMMENDATIONS
FOR
U
NUSED
I
NPUT
AND
O
UTPUT
P
INS
O
UTPUTS
:
LVCMOS O
UTPUT
:
All unused LVCMOS output can be left floating. We
recommend that there is no trace attached.
87004AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
11
Integrated
Circuit
Systems, Inc.
ICS87004I
1:4, D
IFFERENTIAL
-
TO
-LVCMOS/LVTTL
Z
ERO
D
ELAY
C
LOCK
G
ENERATOR
F
IGURE
3C. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3B. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVPECL D
RIVER
F
IGURE
3D. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
3.3V LVDS D
RIVER
3.3V
R1
50
R3
50
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
3.3V
Input
R2
50
Zo = 50 Ohm
Input
HiPerClockS
CLK
nCLK
3.3V
R3
125
R2
84
Zo = 50 Ohm
3.3V
R4
125
LVPECL
R1
84
3.3V
D
IFFERENTIAL
C
LOCK
I
NPUT
I
NTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 3A to 3D show inter-
face examples for the HiPerClockS CLK/nCLK input driven by
the most common driver types. The input interfaces suggested
F
IGURE
3A. H
I
P
ER
C
LOCK
S CLK/
N
CLK I
NPUT
D
RIVEN
BY
ICS H
I
P
ER
C
LOCK
S LVHSTL D
RIVER
here are examples only. Please consult with the vendor of the
driver component to confirm the driver termination requirements.
For example in
Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
R2
50
Input
LVHSTL Driver
ICS
HiPerClockS
R1
50
LVHSTL
3.3V
Zo = 50 Ohm
Zo = 50 Ohm
HiPerClockS
CLK
nCLK
Zo = 50 Ohm
R1
100
3.3V
LVDS_Driv er
Zo = 50 Ohm
Receiv er
CLK
nCLK
3.3V
8308AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
12
Integrated
Circuit
Systems, Inc.
ICS8308I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
/LVCMOS-
TO
-LVCMOS F
ANOUT
B
UFFER
S
CHEMATIC
E
XAMPLE
Figure 3 shows a schematic example of the ICS8308I. In this
example, the LVCMOS_CLK input is selected. The decoupling
F
IGURE
3. ICS8308I LVPECL B
UFFER
S
CHEMATIC
E
XAMPLE
C4
0.1u
(U1,9)
R1
43
VDD
Zo = 50 Ohm
Zo = 50 Ohm
(U1,16)
R10
1K
R11
43
C2
0.1u
C3
0.1u
VDD
(U1,20)
U1
ICS8308I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Q0
GND
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
VDD
GND
Q1
VDDO
Q7
GND
Q6
VDDO
Q5
GND
Q4
VDDO
Q3
GND
Q2
VDDO
VDD=3.3V
R9
1K
(U1,12)
R8
43
Ro ~ 7 Ohm
3.3V_LVCMOS
3.3V LVCMOS/LVTTL
C5
0.1u
R12
1K
VDD
(U1,24)
Zo = 50 Ohm
VDD
VDD
3.3V LVCMOS/LVTTL
C1
0.1u
capacitors should be physically located near the power pin.
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8308I is: 1040
T
ABLE
6.
JA
VS
. A
IR
F
LOW
T
ABLE
FOR
24 L
EAD
TSSOP
JA
by Velocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
70C/W
63C/W
60C/W
8308AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
13
Integrated
Circuit
Systems, Inc.
ICS8308I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
/LVCMOS-
TO
-LVCMOS F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
FOR
24 L
EAD
TSSOP
T
ABLE
7. P
ACKAGE
D
IMENSIONS
R
EFERENCE
D
OCUMENT
: JEDEC P
UBLICATION
95, MO-153
L
O
B
M
Y
S
s
r
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e
m
i
l
l
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m
u
m
i
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m
u
m
i
x
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N
4
2
A
-
-
0
2
.
1
1
A
5
0
.
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5
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8308AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
14
Integrated
Circuit
Systems, Inc.
ICS8308I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
/LVCMOS-
TO
-LVCMOS F
ANOUT
B
UFFER
T
ABLE
8. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
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E
T
O
N
8308AGI
www.icst.com/products/hiperclocks.html
REV. B JULY 25, 2005
15
Integrated
Circuit
Systems, Inc.
ICS8308I
L
OW
S
KEW
, 1-
TO
-8
D
IFFERENTIAL
/LVCMOS-
TO
-LVCMOS F
ANOUT
B
UFFER
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