8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
1
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
G
ENERAL
D
ESCRIPTION
The ICS8533-11 is a low skew, high performance
1-to-4 Crystal Oscillator/Differential-to-3.3V
LVPECL fanout buffer and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS8533-11 has select-
able differential clock or crystal inputs. The CLK, nCLK pair
can accept most standard differential input levels. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the ICS8533-11 ideal for those applications demand-
ing well defined performance and repeatability.
F
EATURES
4 differential 3.3V LVPECL outputs
Selectable CLK, nCLK or crystal inputs
CLK, nCLK pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
Maximum output frequency up to 650MHz
Translates any single-ended input signal to 3.3V
LVPECL levels with resistor bias on nCLK input
Output skew: 30ps (maximum)
Part-to-part skew: 150ps (maximum)
Propagation delay: 2ns (maximum)
3.3V operating supply
0C to 70C ambient operating temperature
Industrial temperature information available upon request
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
ICS8533-11
20-Lead TSSOP
6.5mm x 4.4mm x 0.92 Package Body
G Package
Top View
V
EE
CLK_EN
CLK_SEL
CLK
nCLK
XTAL1
XTAL2
nc
nc
V
CC
1
2
3
4
5
6
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8
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10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
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CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
HiPerClockSTM
,&6
CLK
nCLK
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XTAL2
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
0
1
CLK_EN
CLK_SEL
D
Q
LE
REV. D JULY 16, 2001
2
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
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8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
3
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
3A. C
ONTROL
I
NPUT
F
UNCTION
T
ABLE
T
ABLE
3B. C
LOCK
I
NPUT
F
UNCTION
T
ABLE
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Enabled
Disabled
nCLK
CLK
CLK_EN
nQ0 - nQ3
Q0 - Q3
F
IGURE
1 - CLK_EN T
IMING
D
IAGRAM
REV. D JULY 16, 2001
4
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
CCx
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, V
O
-0.5V to V
CC
+ 0.5V
Package Thermal Impedance,
JA
73.2C/W (0lfpm)
Storage Temperature, T
STG
-65C to 150C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those
listed in the
DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
T
ABLE
4B. LVCMOS / LVTTL DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
T
ABLE
4C. D
IFFERENTIAL
DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
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A
8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
5
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
4D. LVPECL DC C
HARACTERISTICS
,
V
CC
= 3.3V5%, T
A
= 0C
TO
70C
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REV. D JULY 16, 2001
6
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
P
ARAMETER
M
EASUREMENT
I
NFORMATION
F
IGURE
3 - D
IFFERENTIAL
I
NPUT
L
EVEL
CLK
nCLK
V
CC
V
EE
V
CMR
Cross Points
V
PP
F
IGURE
2 - O
UTPUT
L
OAD
T
EST
C
IRCUIT
SCOPE
Qx
nQx
LVPECL
V
CC
V
CC
=
2V
V
EE
=
-1.3V 0.135V
8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
7
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
F
IGURE
7 - odc & t
PERIOD
Pulse Width
t
PERIOD
t
PW
t
PERIOD
odc =
CLK, Q0 - Q3
nCLK, nQ0 - nQ3
F
IGURE
6 - P
ROPAGATION
D
ELAY
t
PD
CLK
nCLK
Q0 - Q3
nQ0 - nQ3
Clock Inputs
and Outputs
20%
80%
20%
80%
t
R
t
F
V
S W I N G
F
IGURE
5 - I
NPUT
AND
O
UTPUT
R
ISING
/F
ALL
T
IME
F
IGURE
4 - O
UTPUT
S
KEW
tsk(o)
Qx
nQx
Qy
nQy
REV. D JULY 16, 2001
8
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
A
PPLICATION
I
INFORMATION
C
RYSTAL
O
SCILLATOR
C
IRCUIT
F
REQUENCY
F
INE
T
UNING
A crystal can be characterized for either series or parallel mode operation. The ICS8533-11 and ICS8535-11 fanout buffers have
built-in crystal oscillator circuits that can accept either a series or parallel crystal without additional components. The frequency
accuracy provided by this configuration is sufficient for most computer applications.
For applications requiring highly accurate clock frequencies, the output frequency can be fine tuned by inserting a small series
capacitor C1 at the XTAL1 input (Pin 6 for ICS8533-11) as shown in
Figure 8. This fine tuning approach can be applied in either
parallel or series crystal. The C1 value depends on the crystal type, frequency and the board layout. The parallel crystal fine
tuning results in smaller ppm and better performance. It is difficult to provide the precise value of C1. This section provides
recommended series capacitor C1 values to start with. This example uses 18pF parallel crystals.
Figure 9shows the suggested series capacitor value for a parallel crystal. For a 16.666 MHz crystal, the recommended C1 value is
about 33pF.
Figure 10 shows frequency accuracy versus series capacitance for 19.44MHz, 16.666MHz and 15MHz crystals. As seen from this
figure, a 24pF, 33pF and 43pF series capacitor is used to achieve the lowest ppm error for 19.44MHz, 16.666MHz and 15MHz
respectively.
Figure 11 shows the experiment results of crystal oscillator frequency drift due to temperature variation.
X1
U1
XTAL2
XTAL1
C1
F
IGURE
8 - C
RYSTAL
I
NTERFACE
WITH
S
ERIES
C
APACITOR
C1
.
8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
9
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
14.318
15.000
16.666
19.440
20.000
24.000
0
10
20
30
40
50
60
14
15
16
17
18
19
20
21
22
23
24
25
Crystal Frequency (MHz)
Ser
i
es C
a
paci
t
o
r
,
C
1
(
p
F
)
F
IGURE
9 - S
UGGESTED
S
ERIES
C
APACITOR
C1
FOR
P
ARALLEL
C
RYSTAL
-100
-80
-60
-40
-20
0
20
40
60
80
100
0
10
20
30
40
50
60
Series Capacitor, C1 (pF)
Fr
equenc
y
A
ccur
a
c
y
(
ppm
)
19.44MHz
16.666MHz
15.00MHz
F
IGURE
10 - F
REQUENCY
A
CCURACY
FOR
P
ARALLEL
C
RYSTAL
U
SING
S
ERIES
C
APACITOR
C1
REV. D JULY 16, 2001
10
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
-60
-40
-20
0
20
40
60
0
10
20
30
40
50
60
70
80
Temperature (deg. C)
Fr
equec
y
Dr
i
f
t
e
d (
ppm
)
19.44MHz
16.666MHz
F
IGURE
11 - C
RYSTAL
O
SCILLATOR
C
RCUIT
F
REQUENCY
D
RIFTED
D
UE
TO
T
EMPERATURE
V
ARIATION
W
IRING
THE
D
IFFERENTIAL
I
NPUT
TO
A
CCEPT
S
INGLE
E
NDED
L
EVELS
Figure 12 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
F
IGURE
12: S
INGLE
E
NDED
S
IGNAL
D
RIVING
D
IFFERENTIAL
I
NPUT
R2
1K
V
CC
CLK_IN
+
-
R1
1K
C1
0.1uF
V_REF
8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
11
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
P
OWER
C
ONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8533-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8533-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 3.465V * 50mA = 173.3mW
Power (outputs)
MAX
= 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 4 * 30.2mW = 120.8mW
Total Power
_MAX
(3.465V, with all outputs switching) = 173.3mW + 120.8mW = 294.1mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS
TM
devices is 125C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used
. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 66.6C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70C with all outputs switching is:
70C + 0.294W * 66.6C/W = 89.58C. This is well below the limit of 125C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
Table 7. Thermal Resistance
q
JA
for 20-pin TSSOP, Forced Convection
REV. D JULY 16, 2001
12
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in
Figure 8.
T
o calculate worst case power dissipation into the load, use the following equations which assume a 50
load, and a termination
voltage of V
CC
- 2V.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
)
Pd_L = [(V
OL_MAX
(V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
)
For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
1.0V
Using V
CC_MAX
= 3.465, this results in V
OH_MAX
= 2.465V
For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
1.7V
Using V
CC_MAX
= 3.465, this results in V
OL_MAX
= 1.765V
Pd_H = [(2.465V - (3.465V - 2V))/50
] * (3.465V - 2.465V) = 20mW
Pd_L = [(1.765V - (3.465V - 2V))/50
] * (3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
F
IGURE
13 - LVPECL D
RIVER
C
IRCUIT
AND
T
ERMINATION
Q1
V
OUT
V
CC
RL
50
V
CC
- 2V
8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
13
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
R
ELIABILITY
I
NFORMATION
T
RANSISTOR
C
OUNT
The transistor count for ICS8533-11 is: 428
T
ABLE
8.
JA
VS
. A
IR
F
LOW
T
ABLE
q
JA
by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 114.5C/W
98.0C/W
88.0C/W
Multi-Layer PCB, JEDEC Standard Test Boards
73.2C/W
66.6C/W
63.5C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
REV. D JULY 16, 2001
14
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
P
ACKAGE
O
UTLINE
- G S
UFFIX
T
ABLE
9. P
ACKAGE
D
IMENSIONS
Reference Document: JEDEC Publication 95, MS-153
L
O
B
M
Y
S
s
r
e
t
e
m
i
l
l
i
M
N
I
M
X
A
M
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0
2
A
-
-
0
2
.
1
1
A
5
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.
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5
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8533AG-11
www.icst.com/products/hiperclocks.html
REV. D JULY 16, 2001
15
Integrated
Circuit
Systems, Inc.
ICS8533-11
L
OW
S
KEW
, 1-
TO
-4, C
RYSTAL
O
SCILLATOR
/
D
IFFERENTIAL
-
TO
-3.3V LVPECL F
ANOUT
B
UFFER
T
ABLE
10. O
RDERING
I
NFORMATION
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recom-
mended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
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