87946AYI-147
www.icst.com/products/hiperclocks.html
REV. A APRIL 21, 2003
1
Integrated
Circuit
Systems, Inc.
ICS87946I-147
L
OW
S
KEW
,
1,
2
LVCMOS/LVTTL C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87946I-147 is a low skew, 1, 2
LVCMOS/LVTTL Clock Generator and a member
of the HiPerClockSTM family of High Performance
Clock Solutions from ICS. The ICS87946I-147 has
two selectable single ended clock inputs. The single
ended clock inputs accept LVCMOS or LVTTL input levels. The
low impedance LVCMOS/LVTTL outputs are designed to drive
50
series or parallel terminated transmission lines. The effec-
tive fanout can be increased from 10 to 20 by utilizing the ability
of the outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the 1,
2 or a combination of 1 and 2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
The ICS87946I-147 is characterized at full 3.3V for input V
DD
,
and mixed 3.3V and 2.5V for output operating supply mode. Guar-
anteed bank, output and part-to-part skew characteristics make
the ICS87946I-147 ideal for those clock distribution applications
demanding well defined performance and repeatability.
F
EATURES
10 single ended LVCMOS/LVTTL outputs,
7
typical output impedance
Selectable CLK0 and CLK1 LVCMOS/LVTTL clock inputs
CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
Maximum output frequency: 250MHz
Bank skew: 30ps (maximum)
Output skew: 175ps (maximum)
Part-to-part skew: 850ps (maximum)
Multiple frequency skew: 200ps (maximum)
3.3V input, outputs may be either 3.3V or 2.5V supply
-40C to 85C ambient operating temperature
Pin compatible to the MPC9446 and MPC946
DIV_SELA
DIV_SELB
DIV_SELC
MR/nOE
QA0:QA2
QB0:QB2
QC0:QC3
CLK_SEL
CLK0
CLK1
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
HiPerClockSTM
,&6
0
1
1
2
0
1
0
1
0
1
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
QB0
V
DDB
QB1
GND
QB2
V
DDB
V
DDC
CLK_SEL
V
DD
CLK0
CLK1
DIV_SELA
DIV_SELB
DIV_SELC
GND
QC3
GND
QC2
V
DDC
QC1
GND
QC0
V
DDC
V
DDA
QA2
GND
QA1
V
DDA
QA0
GND
MR/nOE
ICS87946I-147
-
.
-
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
87946AYI-147
www.icst.com/products/hiperclocks.html
REV. A APRIL 21, 2003
3
Integrated
Circuit
Systems, Inc.
ICS87946I-147
L
OW
S
KEW
,
1,
2
LVCMOS/LVTTL C
LOCK
G
ENERATOR
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DD
X
= 3.3V 0.3V, T
A
= -40C
TO
85C
T
ABLE
4B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DD
X
= 3.3V 0.3V, T
A
= -40C
TO
85C
l
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/
R
M
3
.
0
-
8
.
0
V
1
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C
,
0
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L
C
3
.
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,
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L
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D
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O
n
/
R
M
V
D
D
= V
N
I
V
6
.
3
=
0
5
1
A
1
K
L
C
,
0
K
L
C
V
D
D
= V
N
I
V
6
.
3
=
5
A
I
L
I
t
u
p
n
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t
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e
r
r
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C
w
o
L
,
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,
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S
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V
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D
,
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K
L
C
,
C
L
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S
_
V
I
D
E
O
n
/
R
M
V
D
D
,
V
6
.
3
=
V
N
I
V
0
=
5
-
A
1
K
L
C
,
0
K
L
C
V
D
D
,
V
6
.
3
=
V
N
I
V
0
=
0
5
1
-
A
V
H
O
1
E
T
O
N
;
e
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a
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.
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;
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h
t
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m
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p
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u
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:
1
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T
O
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V
o
t
x
D
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.
t
i
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c
r
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V
3
.
3
,
n
o
i
t
c
e
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t
n
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e
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m
a
r
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P
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S
.
2
/
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5 V
Outputs, V
O
-0.5V to V
DDx
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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