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Электронный компонент: ICS9248-112

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Integrated
Circuit
Systems, Inc.
ICS9248-112
Third party brands and names are the property of their respective owners.
Block Diagram
9248- 112 Rev A 2/7/00
Recommended Application:
810/810E type chipset.
Output Features:
2- CPUs @2.5V, up to 150MHz.
9 - SDRAM @ 3.3V, up to150MHz including
1 free running
8 - PCICLK @ 3.3V
1 - IOAPIC @ 2.5V, PCI or PCI/2 MHz
2 - 3V66MHz @ 3.3V, 2X PCI MHz
1- 48MHz, @3.3V fixed.
1- 24MHz, @3.3V fixed
1- REF @3.3V, 14.318MHz.
Features:
Up to 166MHz frequency support
Support FS0-FS3 strapping status bit for I
2
C read back.
Support power management: Through Power down
Mode from I
2
C programming.
Spread spectrum for EMI control ( 0.25% center).
Spread can be enabled or disabled to all 32 frequencies
throuth I
2
C.
Uses external 14.318MHz crystal
Skew Specifications:
CPU CPU: <175ps
SDRAM - SDRAM: < 250ps
3V66 3V66: <175ps
PCI PCI: <500ps
CPU-SDRAM<500ps
For group skew specifications, please refer to group
timing relationship.
Functionality
Pin Configuration
48-Pin 300mil SSOP
* These inputs have a 120K pull up to VDD.
1 These are double strength.
Frequency Generator & Integrated Buffers for Celeron & P
II
/
III
TM
Additional frequencies selectable through I
2
C programming.
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PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
Preliminary Product Preview
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2
ICS9248-112
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
General Description
Pin Configuration
Power Groups
GNDREF, VDDREF = REF0, X1, X2
GNDPCI , VDDPCI = PCICLK [9:0]
GNDSDR, VDDSDR = SDRAM [7:0], SDRAM_F,
supply for PLL core
GND3V66 , VDD3V66 = 3V66
GND48 , VDD48 = 48MHz, 24_48MHz,
VDDLAPIC = IOAPIC
GNDLCPU , VDDLCPU = CPUCLK [1:0]
The ICS9248-112 is the single chip clock solution for designs
using the 810/810E style chipset. It provides all necessary
clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-112
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection.
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background image
3
ICS9248-112
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Write:
background image
4
ICS9248-112
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
Note 1: Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
* These frequencies with spread enabled are equal to original Intel defined frequency with -0.5% down spread.
I
2
C is a trademark of Philips Corporation
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4
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6
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3
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8
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8
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6
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6
8
8
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2
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%
5
2
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+
1
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1
1
0
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0
7
0
0
.
5
0
1
0
0
.
0
7
0
0
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5
3
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5
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7
1
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5
3
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%
5
2
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1
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1
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6
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6
7
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5
1
1
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6
.
6
7
3
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3
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5
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1
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6
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6
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1
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5
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9
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5
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3
t
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4
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2
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B
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0
1
t
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C
%
5
2
.
0
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E
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S
d
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-
1
0
background image
5
ICS9248-112
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
Byte 1: Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
#
3
S
F
6
t
i
B
-
X
#
0
S
F
5
t
i
B
-
X
#
2
S
F
4
t
i
B
7
2
1
z
H
M
4
2
3
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B
6
2
1
z
H
M
8
4
1
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
0
t
i
B
0
3
1
F
_
M
A
R
D
S
Byte 4: Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
)
d
e
v
r
e
s
e
R
(
6
t
i
B
8
1
1
_
6
6
V
3
5
t
i
B
7
1
0
_
6
6
V
3
4
t
i
B
-
X
#
C
I
P
A
O
I
_
Q
E
R
F
3
t
i
B
6
4
1
C
I
P
A
O
I
2
t
i
B
-
X
#
1
S
F
1
t
i
B
3
4
1
1
K
L
C
U
P
C
0
t
i
B
4
4
1
0
K
L
C
U
P
C
Byte 3: PCI, Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
0
2
1
7
K
L
C
I
C
P
6
t
i
B
9
1
1
6
K
L
C
I
C
P
5
t
i
B
7
1
1
5
K
L
C
I
C
P
4
t
i
B
6
1
1
4
K
L
C
I
C
P
3
t
i
B
5
1
1
3
K
L
C
I
C
P
2
t
i
B
3
1
1
2
K
L
C
I
C
P
1
t
i
B
2
1
1
1
K
L
C
I
C
P
0
t
i
B
1
1
1
0
K
L
C
I
C
P
Byte 2: SDRAM, Control Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
1
3
1
7
M
A
R
D
S
6
t
i
B
2
3
1
6
M
A
R
D
S
5
t
i
B
4
3
1
5
M
A
R
D
S
4
t
i
B
5
3
1
4
M
A
R
D
S
3
t
i
B
6
3
1
3
M
A
R
D
S
2
t
i
B
8
3
1
2
M
A
R
D
S
1
t
i
B
9
3
1
1
M
A
R
D
S
0
t
i
B
0
4
1
0
M
A
R
D
S
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inferted logic
load of the input frequency select pin conditions.
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
-
1
d
e
v
r
e
s
e
R
5
t
i
B
-
1
d
e
v
r
e
s
e
R
4
t
i
B
-
1
d
e
v
r
e
s
e
R
3
t
i
B
-
1
d
e
v
r
e
s
e
R
2
t
i
B
-
1
d
e
v
r
e
s
e
R
1
t
i
B
-
1
d
e
v
r
e
s
e
R
0
t
i
B
-
1
d
e
v
r
e
s
e
R
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: Dont write into this register, writing into this
register can cause malfunction