Integrated
Circuit
Systems, Inc.
ICS94206
94206 Rev B 04/26/01
Pin Configuration
Recommended Application:
440BX - VIA Apollo Pro133 - ALI 1631 style chipset.
Output Features:
2 - CPUs @2.5V
1 - IOAPIC @ 2.5V
13 - SDRAM @ 3.3V
6 - PCI @3.3V,
1 - 48MHz, @3.3V
1 - 24MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
Features:
Programmable ouput frequency.
Programmable ouput rise/fall time.
Programmable PCI_F and PCICLK skew.
Spread spectrum for EMI control typically by 7dB to
8dB,
with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
FS pins for frequency select
Key Specifications:
CPU CPU: <175ps
SDRAM - SDRAM: <500ps
PCI PCI: <500ps
CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
Programmable System Frequency Generator for PII/IIITM
Block Diagram
48-Pin 300mil SSOP
CLK_STOP#
PCI_STOP#
PLL2
PLL1
Spread
Spectrum
48MHz
24MHz
IOAPIC
CPUCLK_F
CPUCLK 1
SDRAM (11:0)
PCICLK (4:0)
PCICLKF
SDRAM_F
X1
X2
BUFFER IN
XTAL
OSC
PCI
CLOCK
DIVDER
STOP
STOP
STOP
STOP
SDATA
SCLK
FS(3:0)
MODE
Control
Logic
Config.
Reg.
/2
REF(1:0)
LATCH
POR
2
12
5
4
4
VDD1
*PCI_STOP/REF0
GND
X1
X2
VDD2
*MODE/PCICLK_F
**FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDD2
BUFFER IN
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLK
VDDL1
IOAPIC
REF1/FS2*
GND
CPUCLK_F
CPUCLK1
VDDL2
CLK_STOP#*
SDRAM_F
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
VDD4
48MHz/FS0*
24MHz/FS1*
ICS94206
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
* Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down resistor of 120K to GND
Functionality
3
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3
3
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
2
ICS94206
General Description
Pin Configuration
The ICS94206 is a single chip clock solution for desktop designs using the BX/Apollo Pro133/ALI 1631 style chipset. It provides all
necessary clock signals for such a system.
The ICS94206 belongs to ICS new generation of programmable system clock generators. It employs serial programming I
2
C
interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to
output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also
has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from
over clocking.
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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3
ICS94206
General I
2
C serial interface information for the ICS94206
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending Byte 0 through Byte 20
(see Note)
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends Byte 0 through byte 8 (default)
ICS clock sends Byte 0 through byte X (if X
(H)
was
written to byte 8).
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 18
ACK
Byte 19
ACK
Byte 20
ACK
Stop Bit
How to Write:
*See notes on the following page
.
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
If 7
H
has been written to B6
Byte 7
ACK
If 12
H
has been written to B6
Byte18
ACK
If 13
H
has been written to B6
Byte 19
ACK
If 14
H
has been written to B6
Byte 20
ACK
Stop Bit
How to Read:
4
ICS94206
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for verification.
Readback will support standard SMBUS controller protocol. The number of bytes to readback is defined by writing to
byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiver.
3.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4.
The input is operating at 3.3V logic levels.
5.
The data byte format is 8 bit bytes.
6.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes.
The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
Notes:
Brief I
2
C registers description for ICS94206
Programmable System Frequency Generator
Register N ame
Byte
Description
PWD Default
Functionality & Frequency
Select Register
0
Output frequency, hardware / I
2
C
frequency select, spread spectrum &
output enable control register.
See individual
byte description
Output Control Registers
1-6
Active / inactive output control
registers/latch inputs read back.
See individual
byte description
Vendor ID & Revision ID
Registers
7
Byte 11 bit[7:4] is ICS vendor id - 1001.
Other bits in this register designate device
revision ID of this part.
See individual
byte description
Byte Count
Read Back Register
8
Writing to this register will configure
byte count and how many byte w ill be
read back. Do not write 00
H
to this byte.
08
H
Watchdog Timer
Count Register
9
Writing to this register will configure the
number of seconds for the watchdog
timer to reset.
10
H
Watchdog Control Registers 10 Bit [6:0]
Watchdog enable, watchdog status and
programmable 'safe' frequency' can be
configured in this register.
000,0000
VCO Control Selection Bit
10 Bit [7]
This bit select w hether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
0
VCO Frequency Control
Registers
11-12
These registers control the dividers ratio
into the phase detector and thus control
the V CO output frequency.
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
13-14
These registers control the spread
percentage amount.
Depended on
hardware/byte 0
configuration
Group Skews Control
Registers
15-16
Increment or decrement the group skew
amount as compared to the initial skew .
See individual
byte description
Output Rise/Fall Time
Select Registers
17-20
These registers will control the output
rise and fall time.
See individual
byte description
5
ICS94206
Byte 0: Functionality and frequency select register (Default=0)
Notes:
1.
Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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4
:
7
,
2
(
2
t
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7
t
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B
6
t
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5
t
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B
4
t
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M
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M
1
e
t
o
N
3
S
F
2
S
F
1
S
F
0
S
F
0
0
0
0
0
0
0
.
0
8
0
0
.
0
4
0
0
0
0
1
0
0
.
5
7
0
5
.
7
3
0
0
0
1
0
1
3
.
3
8
5
6
.
1
4
0
0
0
1
1
2
8
.
6
6
1
4
.
3
3
0
0
1
0
0
0
0
.
3
0
1
3
3
.
4
3
0
0
1
0
1
1
0
.
2
1
1
4
3
.
7
3
0
0
1
1
0
1
0
.
8
6
1
0
.
4
3
0
0
1
1
1
3
2
.
0
0
1
1
4
.
3
3
0
1
0
0
0
0
0
.
0
2
1
0
0
.
0
4
0
1
0
0
1
9
9
.
4
1
1
3
3
.
8
3
0
1
0
1
0
9
9
.
9
0
1
6
6
.
6
3
0
1
0
1
1
0
0
.
5
0
1
0
0
.
5
3
0
1
1
0
0
0
0
.
0
4
1
0
0
.
5
3
0
1
1
0
1
0
0
.
0
5
1
0
5
.
7
3
0
1
1
1
0
0
0
.
4
2
1
0
0
.
1
3
0
1
1
1
1
9
9
.
2
3
1
5
2
.
3
3
1
0
0
0
0
0
0
.
5
3
1
5
7
.
3
3
1
0
0
0
1
9
9
.
9
2
1
0
5
.
2
3
1
0
0
1
0
0
0
.
6
2
1
0
5
.
1
3
1
0
0
1
1
0
0
.
8
1
1
3
3
.
9
3
1
0
1
0
0
8
9
.
5
1
1
6
6
.
8
3
1
0
1
0
1
0
0
.
5
9
7
6
.
1
3
1
0
1
1
0
0
0
.
0
9
0
0
.
0
3
1
0
1
1
1
1
0
.
5
8
4
3
.
8
2
1
1
0
0
0
0
0
.
6
6
1
0
5
.
1
4
1
1
0
0
1
1
0
.
0
6
1
0
0
.
0
4
1
1
0
1
0
9
9
.
4
5
1
5
7
.
8
3
1
1
0
1
1
5
9
.
7
4
1
9
9
.
6
3
1
1
1
0
0
8
9
.
5
4
1
0
5
.
6
3
1
1
1
0
1
8
9
.
3
4
1
9
9
.
5
3
1
1
1
1
0
9
9
.
1
4
1
0
5
.
5
3
1
1
1
1
1
1
0
.
8
3
1
0
5
.
4
3
3
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4
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7
,
2
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0
1
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-
0
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%
5
3
.
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1
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-
1
0
6
ICS94206
Byte 1: CPU, Active/Inactive Register
(1= enable, 0 = disable)
Byte 2: PCI, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B
7
1
F
_
K
L
C
I
C
P
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
3
1
1
4
K
L
C
I
C
P
3
t
i
B
2
1
1
3
K
L
C
I
C
P
2
t
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B
1
1
1
2
K
L
C
I
C
P
1
t
i
B
0
1
1
1
K
L
C
I
C
P
0
t
i
B
8
1
0
K
L
C
I
C
P
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
2. Latched Frequency Selects (FS#) will be inverted logic
load of the input frequency select pin conditions.
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B
-
X
#
1
S
F
d
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h
c
t
a
L
2
t
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B
-
1
)
d
e
v
r
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s
e
R
(
1
t
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B
-
X
#
3
S
F
d
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h
c
t
a
L
0
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
Byte 4: Reserved , Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
7
4
1
0
C
I
P
A
O
I
3
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B
6
4
1
1
F
E
R
0
t
i
B
2
1
0
F
E
R
Byte 5: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Byte 3: SDRAM, Active/Inactive Register
(1= enable, 0 = disable)
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
ti
B
-
1
)
d
e
v
r
e
s
e
R
(
6
ti
B
-
X
#
0
S
F
d
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h
c
t
a
L
5
ti
B
6
2
1
z
H
M
8
4
4
ti
B
5
2
1
z
H
M
4
2
3
ti
B
-
1
)
d
e
v
r
e
s
e
R
(
2
ti
B
7
1
,
8
1
,
0
2
,
1
2
1
)
1
1
:
8
(
M
A
R
D
S
1
ti
B
8
2
,
9
2
,
1
3
,
2
3
1
)
7
:
4
(
M
A
R
D
S
0
ti
B
4
3
,
5
3
,
7
3
,
8
3
1
)
3
:
0
(
M
A
R
D
S
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
6
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
5
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
4
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
3
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
2
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
1
t
i
B
-
1
)
e
t
o
N
(
d
e
v
r
e
s
e
R
0
t
i
B
-
0
)
e
t
o
N
(
d
e
v
r
e
s
e
R
Byte 6: Peripheral , Active/Inactive Register
(1= enable, 0 = disable)
Note: This is an unused register writing to this register will not
affect device performance or functinality.
T
I
B
#
N
I
P
D
W
P
N
O
I
T
P
I
R
C
S
E
D
7
t
i
B
-
X
#
2
S
F
d
e
h
c
t
a
L
6
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B
0
4
1
F
_
M
A
R
D
S
2
t
i
B
-
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B
3
4
1
1
K
L
C
U
P
C
0
t
i
B
4
4
1
F
_
K
L
C
U
P
C
7
ICS94206
Byte 7: Vendor ID and Revision ID Register
Byte 8: Byte Count and Read Back Register
Notes:
1. PWD = Power on Default
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
d
e
v
r
e
s
e
R
6
t
i
B
0
d
e
v
r
e
s
e
R
5
t
i
B
0
d
e
v
r
e
s
e
R
4
t
i
B
0
d
e
v
r
e
s
e
R
3
t
i
B
1
d
e
v
r
e
s
e
R
2
t
i
B
0
d
e
v
r
e
s
e
R
1
t
i
B
0
d
e
v
r
e
s
e
R
0
t
i
B
0
d
e
v
r
e
s
e
R
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
D
I
r
o
d
n
e
V
6
t
i
B
0
D
I
r
o
d
n
e
V
5
t
i
B
1
D
I
r
o
d
n
e
V
4
t
i
B
X
D
I
n
o
i
s
i
v
e
R
3
t
i
B
X
D
I
n
o
i
s
i
v
e
R
2
t
i
B
X
D
I
n
o
i
s
i
v
e
R
1
t
i
B
X
D
I
n
o
i
s
i
v
e
R
0
t
i
B
X
D
I
n
o
i
s
i
v
e
R
Byte 11: VCO Frequency Control Register
Note: The decimal representation of these 7 bits (Byte 11
[6:0]) + 2 is equal to the REF divider value .
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
X
0
ti
B
r
e
d
i
v
i
D
O
C
V
6
ti
B
X
6
ti
B
r
e
d
i
v
i
D
F
E
R
5
ti
B
X
5
ti
B
r
e
d
i
v
i
D
F
E
R
4
ti
B
X
4
ti
B
r
e
d
i
v
i
D
F
E
R
3
ti
B
X
3
ti
B
r
e
d
i
v
i
D
F
E
R
2
ti
B
X
2
ti
B
r
e
d
i
v
i
D
F
E
R
1
ti
B
X
1
ti
B
r
e
d
i
v
i
D
F
E
R
0
ti
B
X
0
ti
B
r
e
d
i
v
i
D
F
E
R
Byte 12: VCO Frequency Control Register
Note: The decimal representation of these 9 bits (Byte 12 bit
[7:0] & Byte 11 bit [7] ) + 8 is equal to the VCO divider value.
For example if VCO divider value of 36 is desired, user need
to program 36 - 8 = 28, namely, 0, 00011100 into byte 12 bit
& byte 11 bit 7.
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
8
t
i
B
r
e
d
i
v
i
D
O
C
V
6
t
i
B
X
7
t
i
B
r
e
d
i
v
i
D
O
C
V
5
t
i
B
X
6
t
i
B
r
e
d
i
v
i
D
O
C
V
4
t
i
B
X
5
t
i
B
r
e
d
i
v
i
D
O
C
V
3
t
i
B
X
4
t
i
B
r
e
d
i
v
i
D
O
C
V
2
t
i
B
X
3
t
i
B
r
e
d
i
v
i
D
O
C
V
1
t
i
B
X
2
t
i
B
r
e
d
i
v
i
D
O
C
V
0
t
i
B
X
1
t
i
B
r
e
d
i
v
i
D
O
C
V
Byte 10: Watchdog Timer Count Register
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
ti
B
0
e
s
e
h
t
f
o
n
o
it
a
t
n
e
s
e
r
p
e
r
l
a
m
i
c
e
d
e
h
T
s
m
1
r
o
s
m
0
9
2
o
t
d
n
o
p
s
e
r
r
o
c
s
ti
b
8
e
r
o
f
e
b
ti
a
w
ll
i
w
r
e
m
it
g
o
d
h
c
t
a
w
e
h
t
e
h
t
t
e
s
e
r
d
n
a
e
d
o
m
m
r
a
l
a
o
t
s
e
o
g
ti
tl
u
a
f
e
D
.
g
n
it
t
e
s
e
f
a
s
e
h
t
o
t
y
c
n
e
u
q
e
r
f
6
.
4
=
s
m
0
9
2
X
6
1
s
i
p
u
r
e
w
o
p
t
a
.
s
d
n
o
c
e
s
6
ti
B
0
5
ti
B
0
4
ti
B
1
3
ti
B
0
2
ti
B
0
1
ti
B
0
0
ti
B
0
Note: FS values in bit [0:4] will correspond to Byte 0 FS
values. Default safe frequency is same as 00000 entry in
byte0.
Byte 9: VCO Control Selection Bit &
Watchdog Timer Control Register
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
0
q
e
r
f
5
1
&
4
1
B
=
1
/
q
e
r
f
0
B
/
w
H
=
0
6
t
i
B
0
e
l
b
a
n
e
=
1
/
e
l
b
a
s
i
d
=
0
e
l
b
a
n
E
D
W
5
t
i
B
0
m
r
a
l
a
=
1
/
l
a
m
r
o
n
=
0
s
u
t
a
t
S
D
W
4
t
i
B
0
2
t
i
b
0
e
t
y
B
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
3
t
i
B
0
3
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
2
t
i
B
0
2
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
1
t
i
B
0
1
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
0
t
i
B
0
0
S
F
,
y
c
n
e
u
q
e
r
F
e
f
a
S
D
W
8
ICS94206
Byte 13: Spread Sectrum Control Register
Byte 14: Spread Sectrum Control Register
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
7
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
6
t
i
B
X
6
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
5
t
i
B
X
5
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
4
t
i
B
X
4
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
3
t
i
B
X
3
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
2
t
i
B
X
2
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
1
t
i
B
X
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
0
t
i
B
X
0
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
d
e
v
r
e
s
e
R
6
t
i
B
X
d
e
v
r
e
s
e
R
5
t
i
B
X
d
e
v
r
e
s
e
R
4
t
i
B
X
2
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
3
t
i
B
X
1
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
2
t
i
B
X
0
1
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
1
t
i
B
X
9
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
0
t
i
B
X
8
t
i
B
m
u
r
t
c
e
p
S
d
a
e
r
p
S
Note: Please utilize software utility provided by ICS
Application Engineering to configure spread spectrum.
Incorrect spread percentage may cause system failure.
Byte 15: Output Skew Control
Byte 16: Output Skew Control
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
l
o
r
t
n
o
C
w
e
k
S
F
_
I
C
P
6
t
i
B
5
t
i
B
l
o
r
t
n
o
C
w
e
k
S
}
4
:
0
[
K
L
C
I
C
P
4
t
i
B
3
t
i
B
l
o
r
t
n
o
C
w
e
k
S
F
_
M
A
R
D
S
2
t
i
B
1
t
i
B
l
o
r
t
n
o
C
w
e
k
S
}
7
:
0
[
M
A
R
D
S
0
t
i
B
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
l
o
r
t
n
o
C
w
e
k
S
]
1
1
:
8
[
M
A
R
D
S
6
t
i
B
5
t
i
B
X
d
e
v
r
e
s
e
R
4
t
i
B
X
d
e
v
r
e
s
e
R
3
t
i
B
X
d
e
v
r
e
s
e
R
2
t
i
B
X
d
e
v
r
e
s
e
R
1
t
i
B
X
d
e
v
r
e
s
e
R
0
t
i
B
X
d
e
v
r
e
s
e
R
Byte 17: Output Rise/Fall Time Select Register
Byte 18: Output Rise/Fall Time Select Register
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
F
_
K
L
C
U
P
C
6
t
i
B
5
t
i
B
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
1
K
L
C
U
P
C
4
t
i
B
3
t
i
B
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
F
_
M
A
R
D
S
2
t
i
B
1
t
i
B
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
]
1
1
:
0
[
M
A
R
D
S
0
t
i
B
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
]
4
:
0
{
I
C
P
6
t
i
B
5
t
i
B
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
F
_
I
C
P
4
t
i
B
3
t
i
B
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
z
H
M
8
4
2
t
i
B
1
t
i
B
l
o
r
t
n
o
C
e
t
a
R
w
e
l
S
:
z
H
M
4
2
0
t
i
B
Notes:
1. PWD = Power on Default
2. The power on default for byte 13-20 depends on the harware (latch inputs FS[0:4]) or I
2
C (Byte 0 bit [1:7]) setting. Be sure to read
back and re-write the values of these 8 registers when VCO frequency change is desired for the first pass.
3. If Byte 8 bit 7 is driven to "1" meaning programming is intended, Byte 21-24 will lose their default power up value.
9
ICS94206
VCO Programming Constrains
VCO Frequency ...................... 150MHz to 500MHz
VCO Divider Range ................ 8 to 519
REF Divider Range ................. 2 to 129
Phase Detector Stability .......... 0.3536 to 1.4142
Useful Formula
VCO Frequency = 14.31818 x VCO/REF divider value
Phase Detector Stabiliy = 14.038 x (VCO divider value)
-0.5
Note:
1. User needs to ensure step 3 & 7 is carried out. Systems with wrong spread percentage and/or group to group skew relation
programmed into bytes 13-16 could be unstable. Step 3 & 7 assure the correct spread and skew relationship.
2. If VCO, REF divider values or phase detector stability are out of range, the device may fail to function correctly.
3. Follow min and max VCO frequency range provided. Internal PLL could be unstable if VCO frequency is too fast or too slow.
Use 14.31818MHz x VCO/REF divider values to calculate the VCO frequency (MHz).
4. ICS recommends users, to utilize the software utility provided by ICS Application Engineering to program the VCO
frequency.
5. Spread percent needs to be calculated based on VCO frequency, spread modulation frequency and spreadamount desired. See
Application note for software support.
To program the VCO frequency for over-clocking.
0. Before trying to program our clock manually, consider using ICS provided software utilities for easy programming.
1. Select the frequency you want to over-clock from with the desire gear ratio (i.e. CPU:SDRAM:3V66:PCI ratio) by
writing to byte 0, or using initial hardware power up frequency.
2. Write 0001, 1001 (19
H
) to byte 8 for readback of 21 bytes (byte 0-20).
3. Read back byte 11-20 and copy values in these registers.
4. Re-initialize the write sequence.
5. Write a '1' to byte 9 bit 7 and write to byte 11 & 12 with the desired VCO & REF divider values.
6. Write to byte 13 to 20 with the values you copy from step 3. This maintains the output spread, skew and slew rate.
7. The above procedure is only needed when changing the VCO for the 1st pass. If VCO frequency needed to be changed
again, user only needs to write to byte 11 and 12 unless the system is to reboot.
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
d
e
v
r
e
s
e
R
6
t
i
B
X
d
e
v
r
e
s
e
R
5
t
i
B
X
d
e
v
r
e
s
e
R
4
t
i
B
X
d
e
v
r
e
s
e
R
3
t
i
B
X
d
e
v
r
e
s
e
R
2
t
i
B
X
d
e
v
r
e
s
e
R
1
t
i
B
X
d
e
v
r
e
s
e
R
0
t
i
B
X
d
e
v
r
e
s
e
R
Byte 19: Reserved Register
Note:
Byte 19 and 20 are reserved registers, these are
unused registers writing to these registers will not
affect device performance or functinality.
t
i
B
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
d
e
v
r
e
s
e
R
6
t
i
B
X
d
e
v
r
e
s
e
R
5
t
i
B
X
d
e
v
r
e
s
e
R
4
t
i
B
X
d
e
v
r
e
s
e
R
3
t
i
B
X
d
e
v
r
e
s
e
R
2
t
i
B
X
d
e
v
r
e
s
e
R
1
t
i
B
X
d
e
v
r
e
s
e
R
0
t
i
B
X
d
e
v
r
e
s
e
R
Byte 20: Reserved Register
10
ICS94206
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . 0C to +70C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 115C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%, V
DDL
= 2.5 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+0.3
V
Input Low Voltage
V
IL
V
SS
-0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
-5
5
A
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
-5
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
C
L
= max cap loads;
CPU=66-133 MHz, SDRAM=100 MHz
124
350
CPU=133 MHz, SDRAM=133 MHz
135
500
I
DD2.5OP
C
L
= max cap loads;
18
70
Powerdown Current
I
DD3.3PD
C
L
= 0 pF; Input address to VDD or GND
600
A
Input Frequency
F
i
V
DD
= 3.3 V
14.318
MHz
Pin Inductance
L
pin
7
nH
C
IN
Logic Inputs
5
pF
C
OUT
Output pin capacitance
6
pF
C
INX
X1 & X2 pins
27
45
pF
Transition time
1
T
trans
To 1st crossing of target frequency
3
ms
Settling time
1
T
s
From 1st crossing to 1% target frequency
3
ms
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target frequency
3
ms
t
PZH
,t
PZL
Output enable delay (all outputs)
1
10
ns
t
PHZ
,t
PLZ
Output disable delay (all outputs)
1
10
ns
Skew
1
tcpu-pci
V
T
= 1.5V; V
TL
=1.25V
2.45
4
ns
1
Guaranteed by design, not 100% tested in production.
Delay
1
Input Capacitance
1
Input Low Current
A
I
DD3.3OP
Operating Supply
Current
mA
11
ICS94206
Electrical Characteristics - CPU
T
A
= 0 - 70 C;VDD = 3.3V; V
DDL
= 2.5 V +/-5%; C
L
= 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Impedance
1
R
DSP2B
Vo=V
DD
*(0.5)
13.5
15
45
Output Impedance
1
R
DSN2B
Vo=V
DD
*(0.5)
13.5
16.5
45
Output High Voltage
V
OH2B
I
OH
= -1 mA
2
2.48
V
Output Low Voltage
V
OL2B
I
OL
= 1 mA
0.04
0.4
V
V
OH@MIN
= 1 V
-60
-27
V
OH@MAX
= 2.375V
-27
-7
V
OL@MIN
= 1.2 V
27
63
V
OL@MAX
=0.3V
20
30
Rise Time
1
t
r2B
V
OL
= 0.4 V, V
OH
= 2.0 V
0.4
1.2
1.6
ns
Fall Time
1
t
f2B
V
OH
= 2.0 V, V
OL
= 0.4 V
0.4
0.9
1.6
ns
Duty Cycle
1
d
t2B
V
T
= 1.25 V
45
46.9
55
%
Skew
1
t
sk2B
V
T
= 1.25 V
12.7
175
ps
Jitter, Cycle-to-cycle
1
t
jcyc-cyc2B
V
T
= 1.25 V, CPU 66, SDRAM 100
150
250
ps
1
Guaranteed by design, not 100% tested in production.
mA
mA
Output High Current
I
OH2B
Output Low Current
I
OL2B
Electrical Characteristics - PCI
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%, C
L
= 40 pF for PCI0-1, C
L
= 10 - 30 pF for other PCIs (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
1
R
DSP1
Vo=V
DD
*(0.5)
12
55
Output Impedance
1
R
DSN1
Vo=V
DD
*(0.5)
12
55
Output High Voltage
V
OH1
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= 1 mA
0.55
V
V
OH@MIN
= 1 V
-33
V
OH@MAX
= 3.135V
-33
V
OL@MIN
= 1.95 V
30
V
OL@MAX
=0.4V
38
Rise Time
1
t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V,
0.5
1.5
2
ns
Fall Time
1
t
f1
V
OL
= 2.4 V, V
OH
= 0.4 V, PCI0-3
0.5
1.5
2
ns
Duty Cycle
1
d
t1
V
T
= 1.5 V
45
52.5
55
%
Skew
1
t
sk1
V
T
= 1.5 V
49
500
ps
Jitter, cycle-to-cycle
1
t
jcyc-cyc1
V
T
= 1.5 V
200
500
ps
1
Guaranteed by design, not 100% tested in production.
mA
mA
Output High Current
I
OH1
Output Low Current
I
OL1
12
ICS94206
Electrical Characteristics - SDRAM
T
A
= 0 - 70 C; V
DD
= 3.3 V +/-5%, C
L
= 20 - 30 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
1
R
DSP3
Vo=V
DD
*(0.5)
10
24
Output Impedance
1
R
DSN3
Vo=V
DD
*(0.5)
10
24
Output High Voltage
V
OH3
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL3
I
OL
= 1 mA
0.4
V
V
OH@MIN
= 2 V
-46
V
OH@MAX
= 3.135V
-54
V
OL@MIN
= 1 V
54
V
OL@MAX
=0.4V
53
Rise Time
1
t
r3
V
OL
= 0.4 V, V
OH
= 2.4 V
0.4
0.8
1.6
ns
Fall Time
1
t
f3
V
OH
= 2.4 V, V
OL
= 0.4 V
0.4
0.8
1.6
ns
Duty Cycle
1
d
t3
V
T
= 1.5 V
45
51.7
55
%
Skew
1
t
sk3
V
T
= 1.5 V
166
250
ps
Propagation Delay
Tprop
V
T
= 1.5 V
3.1
5
ns
1
Guaranteed by design, not 100% tested in production.
mA
mA
Output High Current
I
OH3
Output Low Current
I
OL3
Electrical Characteristics - IOAPIC
T
A
= 0 - 70 C; VDD = 3.3V; V
DDL
= 2.5 V +/-5%; C
L
= 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
1
R
DSP4B
Vo=V
DD
*(0.5)
9
3
Output Impedance
1
R
DSN4B
Vo=V
DD
*(0.5)
9
30
Output High Voltage
V
OH4B
I
OH
= -5.5 mA
2
V
Output Low Voltage
V
OL4B
I
OL
= 9 mA
0.4
V
V
OH@MIN
= 1.4 V
-21
V
OH@MAX
= 2.5V
-36
V
OL@MIN
= 1.0 V
36
V
OL@MAX
=0.2V
31
Rise Time
1
t
r4B
V
OL
= 0.4 V, V
OH
= 2.0 V
0.4
0.7
1.6
ns
Fall Time
1
t
f4B
V
OH
= 2.0 V, V
OL
= 0.4 V
0.4
1.1
1.6
ns
Duty Cycle
1
d
t4B
V
T
= 1.25 V
45
53.7
55
%
1
Guaranteed by design, not 100% tested in production.
mA
mA
Output High Current
I
OH4B
Output Low Current
I
OL4B
13
ICS94206
Electrical Characteristics - REF, 24_48MHz, 48MHz
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Impedance
1
R
DSP5
V
O
= V
DD
*(0.5)
20
60
Output Impedance
1
R
DSN5
V
O
= V
DD
*(0.5)
20
60
Output High Voltage
V
OH5
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL5
I
OL
= 1 mA
0.4
V
V
OH @ MIN
= 1.0 V
-23
V
OH @ MAX
= 3.135 V
-29
V
OL @ MIN
= 1.95 V
29
V
OL @ MAX
= 0.4 V
27
Rise Time
1
t
r5
V
OL
= 0.4 V, V
OH
= 2.4 V
0.4
2
4
ns
Fall Time
1
t
f5
V
OH
= 2.4 V, V
OL
= 0.4 V
0.4
2
4
ns
Duty Cycle
1
d
t5
V
T
= 1.5 V
45
53
55
%
V
T
= 1.5 V, Fixed clocks
200
500
V
T
= 1.5 V, Ref clocks
1032
1250
1
Guaranteed by design, not 100% tested in production.
Jitter, cycle-to-cycle
1
t
jcyc-cyc5
ps
Output High Current
I
OH5
mA
Output Low Current
I
OL5
mA
14
ICS94206
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) on the ICS94206
serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage) that
is present on these pins at this time is read and stored into a 5-
bit internal data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In this
mode the pins produce the specified buffered clocks to external
loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
W
8.2K
W
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
15
ICS94206
CLK_STOP# Timing Diagram
CLK_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CLK_STOP# is synchronized by the ICS94206. The minimum that the CPU clock is enabled (CLK_STOP# high pulse) is 100 CPU
clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state
and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than 4 CPU clocks and
CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CLK_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS94206.
3. IOAPIC output is Stopped Glitch Free by CLK_STOP# going low.
4. SDRAM-F output is controlled by Buffer in signal, not affected by the ICS94206
CLK_STOP# signal. SDRAM's are controlled as shown.
5. All other clocks continue to run undisturbed.
PCICLK
SDRAM
CPUCLK
CPUCLK _F
SDRAM_F
IOAPIC
PCI_STOP# (High)
CLK_STOP#
INTERNAL
CPUCLK
16
ICS94206
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS94206. It is used to turn off the PCICLK clocks for low power operation. PCI_STOP#
is synchronized by the ICS94206 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse) is at least
10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK clock on
latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS94206 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS94206.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
17
ICS94206
Group Offset Waveforms
Cycle Repeats
0ns
CPU 66MHz
CPU 100MHz
CPU 133MHz
SDRAM 133MHz
SDRAM 100MHz
3.5V 66MHz
PCI 33MHz
APIC 33MHz
REF 14.318MHz
USB 48MHz
10ns
20ns
30ns
40ns
18
ICS94206
Ordering Information
ICS94206yF-T
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - T
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
h x 45
h x 45
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
- C -
b
.10 (.004) C
.10 (.004) C
c
L
300 mil SSOP Package
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.03
10.68
.395
.420
E1
7.40
7.60
.291
.299
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
0
8
0
8
MIN
MAX
MIN
MAX
48
15.75
16.00
.620
.630
10-0034
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
SEE VARIATIONS
SEE VARIATIONS
0.635 BASIC
0.025 BASIC
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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