94228
Integrated
Circuit
Systems, Inc.
ICS94228
Third party brands and names are the property of their respective owners.
Block Diagram
94228 Rev C 05/31/01
Functionality
Pin Configuration
48-Pin 300mil SSOP
Recommended Application:
VIA KT266 style chipset
Output Features:
1 - Differential pair open drain CPU clocks @ 2.5V
1 - Differential pair push-pull CPU clocks @ 2.5V
11 - PCI including 1 free running and 1 early @ 3.3V
1 - 48MHz, @ 3.3V fixed
1 - 24/48MHz @ 3.3V
3 - REF @ 3.3V, 14.318MHz.
Features:
Programmable output frequency.
Programmable output rise/fall time.
Programmable slew and skew control for CPUCLK,
PCICLK, AGP, REF, 48MHz and 24_48MHz.
Real time system reset output.
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
Skew Specifications:
CPU - CPU: <175ps
PCI - PCI: <500ps
CPU (early - PCI: min=1.0ns, max=2.0ns
CPU cycle to cycle jitter: <250ps
Programmable System Clock Chip for AMD - K7TM processor
* Internal Pull-up Resistor of 120K to VDD
VDDREF
GND
X1
X2
AVDD48
*FS2/48MHz
*FS3/24_48MHz
GND
PCICLK_F
*SEL24_48#/PCICLK0
PCICLK1
GND
PCICLK2
PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
PCILCK8
PCICLK9_E
VDDPCI
SRESET#
REF0/
REF1/FS1*
REF_F
REF_STOP#*
AGP_STOP#*
GND
CPUCLKT0
CPUCLKC0
VDDL
CPUCLK_CST0
CPUCLK_CSC0
GND
CPU_STOP#*
PCI_STOP#*
PD#*
AVDD
AGND
SDATA
SCLK
GND
AGP2
AGP1
AGP0
VDDAGP
FS0*
ICS94228
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL24_48#
PLL2
PLL1
Spread
Spectrum
48MHz (1:0)
24_48MHz
PCICLK (8:0)
AGP (2:0)
PCICLK_F
REF_F
PCICLK9_E
SRESET#
3
9
2
2
X1
X2
XTAL
OSC
CPU
DIVDER
CPU
DIVDER
PCI
DIVDER
AGP
DIVDER
Stop
Stop
Stop
Stop
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
CPU_STOP#
AGP_STOP#
REF_STOP#
Control
Logic
Config.
Reg.
/ 2
REF (1:0)
CPUCLKT0
CPUCLKC0
CPUCLK_CST0
CPUCLK_CSC0
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PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
Preliminary Product Preview
2
ICS94228
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
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ICS94228
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
General Description
The ICS94228 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all clocks
required for such a system.
The ICS94228 belongs to ICS new generation of programmable system clock generators. It employs serial programming I
2
C
interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring
output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks.
This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system
become unstable from over clocking.
SRESET# Signal Description
The SRESET# signal from ICS94228 system clock generator is a real time active low pulse that can be used to reset the system.
The Open-Drain Nch output Reset# pin needs to be tied to the system reset line which has a pull-up resistor. When activated,
the SRESET# output will be driven to a low with a 32ms pulse width.
4
ICS94228
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
General I
2
C serial interface information for the ICS94228
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending Byte 0 through Byte 16
(see Note 2)
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends Byte 0 through byte 6 (default)
ICS clock sends Byte 0 through byte X (if X
(H)
was
written to byte 6).
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
*See notes on the following page
.
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 14
ACK
Byte 15
ACK
Byte 16
ACK
Stop Bit
How to Write:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
If 7
H
has been written to B6
Byte 7
ACK
If 1A
H
has been written to B6
Byte 14
ACK
If 1B
H
has been written to B6
Byte 15
ACK
If 1C
H
has been written to B6
Byte 16
ACK
Stop Bit
How to Read:
5
ICS94228
Preliminary Product Preview
Third party brands and names are the property of their respective owners.
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Readback will support standard SMBUS controller protocol. The number of bytes to readback is
defined by writing to byte 8.
2.
When writing to byte 11 - 12, and byte 13 - 14, they must be written as a set. If for example, only byte 14 is written
but not 15, neither byte 14 or 15 will load into the receiver.
3.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
4.
The input is operating at 3.3V logic levels.
5.
The data byte format is 8 bit bytes.
6.
To simplify the clock generator I
2
C interface, the protocol is set to use only Block-Writes from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete
byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored
for those two bytes. The data is loaded until a Stop sequence is issued.
7.
At power-on, all registers are set to a default condition, as shown.
Notes:
Brief I
2
C registers description for ICS94228
Programmable System Frequency Generator
R egister Name
Byte
Description
PWD Default
Functionality & Frequency
Select Register
0
O utput frequency, hardw are / I
2
C
frequency select, spread spectrum &
output enable control register.
See individual
byte description
Output Control Registers
1, 2, 3
A ctive / inactive output control
registers/latch inputs read back.
See individual
byte description
Vendor ID & Revision ID
Registers
5, 6, 7
Byte 11 bit[7:4] is ICS vendor id - 1001.
O ther bits in this register designate device
revision ID of this part.
See individual
byte description
Byte Count
Read Back Register
8
Writing to this register w ill configure
byte count and how many byte will be
read back. Do not w rite 00
H
to this byte.
08
H
Watchdog Enable Register
4
Writing to this register w ill configure the
number of seconds for the watchdog
timer to reset.
10
H
Watchdog Control Registers
Watchdog enable, w atchdog status and
programmable 'safe' frequency' can be
configured in this register.
000,0000
VCO Control Selection Bit
4, 5
This bit select whether the output
frequency is control by hardware/byte 0
configurations or byte 11&12
programming.
0
VCO Frequency Control
Registers
9, 10
These registers control the dividers ratio
into the phase detector and thus control
the VCO output frequency.
Depended on
hardware/byte 0
configuration
Spread Spectrum Control
Registers
11, 12
These registers control the spread
percentage amount.
Depended on
hardware/byte 0
configuration
Group Skew s Control
Registers
13, 14
Increment or decrement the group skew
amount as compared to the initial skew.
See individual
byte description
Output Rise/Fall Time
Select Registers
15, 16
These registers will control the output
rise and fall time.
See individual
byte description
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