Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Block Diagram
Pin Configuration
Recommended Application:
CK-408 clock with driven mode only for Brookdale chipset with
P4 processor.
Output Features:
3 - Pairs of differential CPU clocks @ 3.3V
4 - 3V66 @ 3.3V
10 - PCI @ 3.3V
1 - 48MHz @ 3.3V fixed
1 - 24_48MHz selectable output @ 3.3V
2 - REF @ 3.3V, 14.318MHz
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Supports I
2
C Index read/write and block read/write
operations.
Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
Programmable Timing Control HubTM for P
4
TM
Frequency Table
PLL2
PLL2
PLL1
PLL1
Spread
Spread
Spectr
Spectrum
um
48MHz
48MHz
PCICLK (6:0), PCICLK_F (1:0)
PCI
3V66 (3:0)
3V66 (3:0)
24_48MHz
24_48MHz
X1
X1
X2
X2
XT
XTAL
AL
OSC
OSC
CPU
CPU
DIVDER
DIVDER
PCI
PCI
DIVDER
DIVDER
3V66
3V66
DIVDER
DIVDER
PD#
PD#
MUL
MULTSEL(1:0)
TSEL(1:0)
SD
SDATA
SCLK
SCLK
Vtt_PWRGD#
Vtt_PWRGD#
FS (4:0)
FS (4:0)
I REF
I REF
RESET#
RESET#
Control
Control
Logic
Logic
Config.
Config.
Reg.
Reg.
REF (1:0)
REF (1:0)
3
10
10
4
3
CPUCLKT (2:0)
CPUCLKT (2:0)
CPUCLKC (2:0)
CPUCLKC (2:0)
/ 2
/ 2
*MULTSEL1/REF1 1
48 REF0/MULTSEL0*
VDDREF 2
47 GNDREF
X1 3
46 VDDCPU
X2 4
45 CPUCLKT2
GND 5
44 CPUCLKC2
*FS2/PCICLK_F0 6
43 GNDCPU
*FS3/PCICLK_F1 7
42 PD#
PCICLK_F2 8
41 CPUCLKT0
VDDPCI 9
40 CPUCLKC0
*FS4/PCICLK0 10
39 VDDCPU
PCICLK1 11
38 CPUCLKT1
PCICLK2 12
37 CPUCLKC1
GND 13
36 GNDCPU
PCICLK3 14
35 IREF
PCICLK4 15
34 AVDD
PCICLK5 16
33 GND
PCICLK6 17
32 VDD3V66
VDDPCI 18
31 3V66_0
Vttpwr_GD# 19
30 3V66_1
RESET# 20
29 GND
GND 21
28 3V66_2
*FS0/48MHz 22
27 3V66_3
*FS1/24_48MHz 23
26 SCLK
AVDD48 24
25 SDATA
48-SSOP
* Internal Pull-Up Resistor of 120K to VDD
I
C
S950208
Bit2
Bit7
Bit6
Bit5
Bit4
CPU
3V66
PCI
FS4
FS3
FS2
FS1
FS0
MHz
MHz
MHz
0
0
0
0
0
102.00
68.00
34.00
0
0
0
0
1
105.00
70.00
35.00
0
0
0
1
0
108.00
72.00
36.00
0
0
0
1
1
111.00
74.00
37.00
0
0
1
0
0
114.00
76.00
38.00
0
0
1
0
1
117.00
78.00
39.00
0
0
1
1
0
120.00
80.00
40.00
0
0
1
1
1
123.00
82.00
41.00
0
1
0
0
0
126.00
72.00
36.00
0
1
0
0
1
130.00
74.30
37.10
0
1
0
1
0
136.00
68.00
34.00
0
1
0
1
1
140.00
70.00
35.00
0
1
1
0
0
144.00
72.00
36.00
0
1
1
0
1
148.00
74.00
37.00
0
1
1
1
0
152.00
76.00
38.00
0
1
1
1
1
156.00
78.00
39.00
1
0
0
0
0
160.00
80.00
40.00
1
0
0
0
1
164.00
82.00
41.00
1
0
0
1
0
166.60
66.60
33.30
1
0
0
1
1
170.00
68.00
34.00
1
0
1
0
0
175.00
70.00
35.00
1
0
1
0
1
180.00
72.00
36.00
1
0
1
1
0
185.00
74.00
37.00
1
0
1
1
1
190.00
76.00
38.00
1
1
0
0
0
66.80
66.80
33.40
1
1
0
0
1
100.20
66.80
33.40
1
1
0
1
0
133.60
66.80
33.40
1
1
0
1
1
200.40
66.80
33.40
1
1
1
0
0
66.60
66.60
33.30
1
1
1
0
1
100.00
66.60
33.30
1
1
1
1
0
200.00
66.60
33.30
1
1
1
1
1
133.33
66.60
33.30
2
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Pin Description
The ICS950208 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR
memory. It provides all necessary clock signals for such a system.
The ICS950208 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). ICS is the
first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting
under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment. With
all these programmable features ICS's, TCH makes mother board testing, tuning and improvement very simple.
General Description
PIN
PIN
PIN
#
NAME
TYPE
1
*MULTSEL1/REF1
I/O
3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference
clock.
2
VDDREF
PWR Ref, XTAL power supply, nominal 3.3V
3
X1
IN
Crystal input, Nominally 14.318MHz.
4
X2
OUT Crystal output, Nominally 14.318MHz
5
GND
PWR Ground pin.
6
*FS2/PCICLK_F0
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
7
*FS3/PCICLK_F1
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
8
PCICLK_F2
OUT Free running PCI clock not affected by PCI_STOP# .
9
VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
10
*FS4/PCICLK0
#N/A #N/A
11
PCICLK1
OUT PCI clock output.
12
PCICLK2
OUT PCI clock output.
13
GND
PWR Ground pin.
14
PCICLK3
OUT PCI clock output.
15
PCICLK4
OUT PCI clock output.
16
PCICLK5
OUT PCI clock output.
17
PCICLK6
OUT PCI clock output.
18
VDDPCI
PWR Power supply for PCI clocks, nominal 3.3V
19
Vttpwr_GD#
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are
valid and are ready to be sampled. This is an active low input.
20
RESET#
OUT
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
21
GND
PWR Ground pin.
22
*FS0/48MHz
I/O
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
23
*FS1/24_48MHz
I/O
Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V.
24
AVDD48
PWR Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
DESCRIPTION
~ This output has 2X drive
3
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Pin Description (Continued)
PIN PIN
PIN
#
NAME
TYPE
25
SDATA
I/O
Data pin for I2C circuitry 5V tolerant
26
SCLK
IN
Clock pin of I2C circuitry 5V tolerant
27
3V66_3
OUT 3.3V 66.66MHz clock output
28
3V66_2
OUT 3.3V 66.66MHz clock output
29
GND
PWR Ground pin.
30
3V66_1
OUT 3.3V 66.66MHz clock output
31
3V66_0
OUT 3.3V 66.66MHz clock output
32
VDD3V66
PWR Power pin for the 3V66 clocks.
33
GND
PWR Ground pin.
34
AVDD
PWR 3.3V Analog Power pin for Core PLL
35
IREF
OUT
This pin establishes the reference current for the differential current-mode output pairs. This
pin requires a fixed precision resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
36
GNDCPU
PWR Ground pin for the CPU outputs
37
CPUCLKC1
OUT
"Complimentary" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
38
CPUCLKT1
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
39
VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
40
CPUCLKC0
OUT
"Complimentary" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
41
CPUCLKT0
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
42
PD#
IN
Asynchronous active low input pin used to power down the device into a low power state. The
internal clocks are disabled and the VCO and the crystal are stopped. The latency of the
power down will not be greater than 1.8ms.
43
GNDCPU
PWR Ground pin for the CPU outputs
44
CPUCLKC2
OUT
"Complimentary" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
45
CPUCLKT2
OUT
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
46
VDDCPU
PWR Supply for CPU clocks, 3.3V nominal
47
GNDREF
PWR Ground pin for the REF outputs.
48
REF0/MULTSEL0*
I/O
3.3V LVTTL input for selection the current multiplier for CPU outputs / 14.318 MHz reference
clock.
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
DESCRIPTION
~ This output has 2X drive
4
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Maximum Allowed Current
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CPUCLK Swing Select Functions
5
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
*See notes on the following page
.
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byt
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byt
e
ACK
ACK
6
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Byte 0: Functionality and frequency select register (Default=0)
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
t
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4
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4
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F
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.
2
0
1
0
0
.
8
6
0
0
.
4
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5
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7
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0
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8
0
1
0
0
.
2
7
0
0
.
6
3
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e
t
n
e
C
%
5
2
.
0
-
/
+
0
0
0
1
1
0
0
.
1
1
1
0
0
.
4
7
0
0
.
7
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
0
0
1
0
0
0
0
.
4
1
1
0
0
.
6
7
0
0
.
8
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
0
0
1
0
1
0
0
.
7
1
1
0
0
.
8
7
0
0
.
9
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
0
0
1
1
0
0
0
.
0
2
1
0
0
.
0
8
0
0
.
0
4
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
0
0
1
1
1
0
0
.
3
2
1
0
0
.
2
8
0
0
.
1
4
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
0
1
0
0
0
0
0
.
6
2
1
0
0
.
2
7
0
0
.
6
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
0
1
0
0
1
0
0
.
0
3
1
0
3
.
4
7
0
1
.
7
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
0
1
0
1
0
0
0
.
6
3
1
0
0
.
8
6
0
0
.
4
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
0
1
0
1
1
0
0
.
0
4
1
0
0
.
0
7
0
0
.
5
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
0
1
1
0
0
0
0
.
4
4
1
0
0
.
2
7
0
0
.
6
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
0
1
1
0
1
0
0
.
8
4
1
0
0
.
4
7
0
0
.
7
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
0
1
1
1
0
0
0
.
2
5
1
0
0
.
6
7
0
0
.
8
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
0
1
1
1
1
0
0
.
6
5
1
0
0
.
8
7
0
0
.
9
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
0
0
0
0
0
.
0
6
1
0
0
.
0
8
0
0
.
0
4
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
0
0
1
0
0
.
4
6
1
0
0
.
2
8
0
0
.
1
4
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
0
1
0
0
6
.
6
6
1
0
6
.
6
6
0
3
.
3
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
0
1
1
0
0
.
0
7
1
0
0
.
8
6
0
0
.
4
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
1
0
0
0
0
.
5
7
1
0
0
.
0
7
0
0
.
5
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
1
0
1
0
0
.
0
8
1
0
0
.
2
7
0
0
.
6
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
1
1
0
0
0
.
5
8
1
0
0
.
4
7
0
0
.
7
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
0
1
1
1
0
0
.
0
9
1
0
0
.
6
7
0
0
.
8
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
0
0
0
0
8
.
6
6
0
8
.
6
6
0
4
.
3
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
0
0
1
0
2
.
0
0
1
0
8
.
6
6
0
4
.
3
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
0
1
0
0
6
.
3
3
1
0
8
.
6
6
0
4
.
3
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
0
1
1
0
4
.
0
0
2
0
8
.
6
6
0
4
.
3
3
d
a
e
r
p
s
r
e
t
n
e
C
%
5
2
.
0
-
/
+
1
1
1
0
0
0
6
.
6
6
0
6
.
6
6
0
3
.
3
3
d
a
e
r
p
s
n
w
o
D
%
5
.
0
-
o
t
0
1
1
1
0
1
0
0
.
0
0
1
0
6
.
6
6
0
3
.
3
3
d
a
e
r
p
s
n
w
o
D
%
5
.
0
-
o
t
0
1
1
1
1
0
0
0
.
0
0
2
0
6
.
6
6
0
3
.
3
3
d
a
e
r
p
s
n
w
o
D
%
5
.
0
-
o
t
0
1
1
1
1
1
3
3
.
3
3
1
0
6
.
6
6
0
3
.
3
3
d
a
e
r
p
s
n
w
o
D
%
5
.
0
-
o
t
0
3
t
i
B
s
t
u
p
n
i
d
e
h
c
t
a
l
,
t
c
e
l
e
s
e
r
a
w
d
r
a
h
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
0
4
:
7
,
2
t
i
B
y
b
d
e
t
c
e
l
e
s
s
i
y
c
n
e
u
q
e
r
F
-
1
0
1
t
i
B
l
a
m
r
o
N
-
0
e
l
b
a
n
e
m
u
r
t
c
e
p
s
d
a
e
r
p
S
-
1
0
0
t
i
B
s
t
u
p
n
i
h
c
t
a
l
y
b
d
e
t
c
e
l
e
s
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b
ll
i
w
y
c
n
e
u
q
e
r
f
e
f
a
s
g
o
d
h
c
t
a
W
-
0
)
0
:
4
(
t
i
b
0
1
e
t
y
B
y
b
d
e
m
m
a
r
g
o
r
p
e
b
ll
i
w
y
c
n
e
u
q
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r
f
e
f
a
s
g
o
d
h
c
t
a
W
-
1
0
7
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Byte 1: Output Control Register
(1 = enable, 0 = disable)
Byte 3: Output Control Register
(1 = enable, 0 = disable)
Byte 2: Output Control Register
(1 = enable, 0 = disable)
Byte 4: Output Control Register
(1 = enable, 0 = disable)
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
4
4
,
5
4
1
2
C
/
T
U
P
C
6
t
i
B
7
3
,
8
3
1
1
C
/
T
U
P
C
5
t
i
B
0
4
,
1
4
1
0
C
/
T
U
P
C
4
t
i
B
-
X
k
c
a
b
d
a
e
R
4
S
F
3
t
i
B
-
X
k
c
a
b
d
a
e
R
3
S
F
2
t
i
B
-
X
k
c
a
b
d
a
e
R
2
S
F
1
t
i
B
-
X
k
c
a
b
d
a
e
R
1
S
F
0
t
i
B
-
X
k
c
a
b
d
a
e
R
0
S
F
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
-
1
d
e
v
r
e
s
e
R
6
t
i
B
7
1
1
6
_
K
L
C
I
C
P
5
t
i
B
6
1
1
5
_
K
L
C
I
C
P
4
t
i
B
5
1
1
4
_
K
L
C
I
C
P
3
t
i
B
4
1
1
3
_
K
L
C
I
C
P
2
t
i
B
2
1
1
2
_
K
L
C
I
C
P
1
t
i
B
1
1
1
1
_
K
L
C
I
C
P
0
t
i
B
0
1
1
0
_
K
L
C
I
C
P
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
3
2
1
z
H
M
8
4
-
4
2
6
t
i
B
2
2
1
z
H
M
8
4
5
t
i
B
-
1
e
l
b
a
s
i
D
=
0
,
e
l
b
a
n
E
=
1
t
c
e
t
e
d
t
f
i
h
s
r
a
e
g
t
e
s
e
R
4
t
i
B
-
X
d
e
v
r
e
s
e
R
3
t
i
B
-
0
z
H
M
8
4
=
1
;
z
H
M
4
2
=
0
;
8
4
_
4
2
l
e
S
2
t
i
B
8
1
2
F
_
K
L
C
I
C
P
1
t
i
B
7
1
1
F
_
K
L
C
I
C
P
0
t
i
B
6
1
0
F
_
K
L
C
I
C
P
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
-
X
)
k
c
a
b
d
a
e
r
(
0
L
E
S
i
t
l
u
M
6
t
i
B
-
X
)
k
c
a
b
d
a
e
R
(
1
L
E
S
i
t
l
u
M
5
t
i
B
1
3
1
0
-
6
6
V
3
4
t
i
B
0
3
1
1
-
6
6
V
3
3
t
i
B
8
4
1
0
F
E
R
2
t
i
B
1
1
1
F
E
R
1
t
i
B
7
2
1
3
_
6
6
V
3
0
t
i
B
8
2
1
2
_
6
6
V
3
Notes:
1. PWD = Power on Default
2. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
8
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Byte 7: Revision ID and Device ID Register
Byte 8: Byte Count Read Back Register
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
t
i
B
#
n
i
P
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
X
1
)
d
e
v
r
e
s
e
R
(
6
t
i
B
X
1
)
d
e
v
r
e
s
e
R
(
5
t
i
B
X
1
)
d
e
v
r
e
s
e
R
(
4
t
i
B
X
1
)
d
e
v
r
e
s
e
R
(
3
t
i
B
X
1
)
d
e
v
r
e
s
e
R
(
2
t
i
B
X
1
)
d
e
v
r
e
s
e
R
(
1
t
i
B
X
1
)
d
e
v
r
e
s
e
R
(
0
t
i
B
X
1
)
d
e
v
r
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s
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R
(
t
i
B
e
m
a
N
D
W
P
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p
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D
7
t
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7
e
t
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B
0
w
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d
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n
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c
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b
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c
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:
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t
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t
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k
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b
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F
0
H
.
s
e
t
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b
5
1
=
6
t
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B
6
e
t
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B
0
5
t
i
B
5
e
t
y
B
0
4
t
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B
4
e
t
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B
0
3
t
i
B
3
e
t
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B
1
2
t
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B
2
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t
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B
1
1
t
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B
1
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t
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1
0
t
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0
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1
t
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m
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7
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7
D
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6
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6
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5
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5
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1
4
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4
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3
t
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3
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1
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t
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9
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Byte 10: Programming Enable bit 8 Watchdog Control Register
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Byte 9: Watchdog Timer Count Register
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10
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Byte 14: Spread Spectrum Control Register
Byte 15: Output Divider Control Register
Byte 13: Spread Spectrum Control Register
Byte 16: Output Divider Control Register
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i
B
2
v
i
D
6
6
V
3
X
1
t
i
B
1
v
i
D
6
6
V
3
X
0
t
i
B
0
v
i
D
6
6
V
3
X
11
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Byte 17: Output Divider Control Register
Byte 18: Group Skew Control Register
Byte 19: Group Skew Control Register
Table 1
Table 2
)
2
:
3
(
v
i
D
0
0
1
0
0
1
1
1
)
0
:
1
(
v
i
D
0
0
2
/
4
/
8
/
6
1
/
1
0
3
/
6
/
2
1
/
4
2
/
0
1
5
/
0
1
/
0
2
/
0
4
/
1
1
7
/
4
1
/
8
2
/
6
5
/
)
2
:
3
(
v
i
D
0
0
1
0
0
1
1
1
)
0
:
1
(
v
i
D
0
0
4
/
8
/
6
1
/
2
3
/
1
0
3
/
6
/
2
1
/
4
2
/
0
1
5
/
0
1
/
0
2
/
0
4
/
1
1
7
/
4
1
/
8
2
/
6
5
/
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
V
N
I
_
)
2
:
3
(
6
6
V
3
X
t
i
b
n
o
i
s
r
e
v
n
I
e
s
a
h
P
)
2
:
3
(
6
6
V
3
6
t
i
B
V
N
I
_
)
0
:
1
(
6
6
V
3
X
t
i
b
n
o
i
s
r
e
v
n
I
e
s
a
h
P
)
0
:
1
(
6
6
V
3
5
t
i
B
V
N
I
_
U
P
C
X
t
i
b
n
o
i
s
r
e
v
n
I
e
s
a
h
P
2
_
K
L
C
U
P
C
4
t
i
B
V
N
I
_
U
P
C
X
t
i
b
n
o
i
s
r
e
v
n
I
e
s
a
h
P
K
L
C
U
P
C
3
t
i
B
3
v
i
D
I
C
P
X
s
t
i
b
4
e
s
e
h
t
a
i
v
d
e
r
u
g
i
f
n
o
c
e
b
n
a
c
o
i
t
a
r
r
e
d
i
v
i
d
k
c
o
l
c
I
C
P
.
2
e
l
b
a
T
o
t
r
e
f
e
r
e
l
b
a
t
n
o
i
t
c
e
l
e
s
r
e
d
i
v
i
d
r
o
F
.
y
ll
a
u
d
i
v
i
d
n
i
.
r
e
d
i
v
i
d
S
F
d
e
h
c
t
a
l
s
i
p
u
r
e
w
o
p
t
a
t
l
u
a
f
e
D
2
t
i
B
2
v
i
D
I
C
P
X
1
t
i
B
1
v
i
D
I
C
P
X
0
t
i
B
0
v
i
D
I
C
P
X
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
1
w
e
k
S
_
U
P
C
0
o
t
t
c
e
p
s
e
r
h
t
i
w
2
T
/
C
K
L
C
U
P
C
e
h
t
y
a
l
e
d
s
t
i
b
2
e
s
e
h
T
)
0
:
1
(
T
/
C
K
L
C
U
P
C
s
p
0
5
7
=
1
1
s
p
0
0
5
=
0
1
s
p
0
5
2
=
1
0
s
p
0
=
0
0
6
t
i
B
0
w
e
k
S
_
U
P
C
1
5
t
i
B
d
e
v
r
e
s
e
R
0
d
e
v
r
e
s
e
R
4
t
i
B
d
e
v
r
e
s
e
R
0
d
e
v
r
e
s
e
R
3
t
i
B
1
w
e
k
S
_
U
P
C
0
e
h
t
y
a
l
e
d
s
t
i
b
2
e
s
e
h
T
)
0
:
1
(
T
/
C
K
L
C
U
P
C
o
t
t
c
e
p
s
e
r
h
t
i
w
k
c
o
l
c
2
T
/
C
K
L
C
U
P
C
s
p
0
5
2
=
1
0
s
p
0
=
0
0
s
p
0
5
7
=
1
1
s
p
0
0
5
=
0
1
2
t
i
B
0
w
e
k
S
_
U
P
C
1
1
t
i
B
d
e
v
r
e
s
e
R
0
d
e
v
r
e
s
e
R
0
t
i
B
d
e
v
r
e
s
e
R
0
d
e
v
r
e
s
e
R
t
i
B
e
m
a
N
D
W
P
e
c
n
e
u
q
e
S
g
n
i
m
m
a
r
g
o
r
P
7
t
i
B
l
o
r
t
n
o
c
s
t
i
b
4
e
s
e
h
T
)
2
:
3
(
6
6
V
3
-
U
P
C
0
0
0 0 0
s
p
0
d
e
v
r
e
s
e
R
6
t
i
B
1
0
1 0 0
s
p
0
5
1
d
e
v
r
e
s
e
R
5
t
i
B
0
1
0 0 0
s
p
0
0
3
d
e
v
r
e
s
e
R
4
t
i
B
0
1
1 0 0
s
p
0
5
4
d
e
v
r
e
s
e
R
3
t
i
B
l
o
r
t
n
o
c
s
t
i
b
4
e
s
e
h
T
)
0
:
1
(
6
6
V
3
-
U
P
C
0
1
1 0
1
s
p
0
0
6
d
e
v
r
e
s
e
R
2
t
i
B
1
1
1 1 0
s
p
0
5
7
d
e
v
r
e
s
e
R
1
t
i
B
0
1
1 1 1
s
p
0
0
9
d
e
v
r
e
s
e
R
0
t
i
B
0
d
e
v
r
e
s
e
R
d
e
v
r
e
s
e
R
12
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Byte 20: Group Skew Control Register
Byte 21: Slew Rate Control Register
Byte 22: Slew Rate Control Register
Byte 23: Slew Rate Control Register
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
1
w
e
l
S
_
2
_
K
L
C
I
C
P
1
.
s
t
i
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
2
K
L
C
I
C
P
k
a
e
w
=
0
1
;
l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
6
t
i
B
1
w
e
l
S
_
2
_
K
L
C
I
C
P
0
5
t
i
B
0
w
e
l
S
_
)
0
:
1
(
F
_
K
L
C
I
C
P
1
.
s
t
i
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
)
0
:
1
(
F
_
K
L
C
I
C
P
k
a
e
w
=
0
1
;
l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
4
t
i
B
0
w
e
l
S
_
)
0
:
1
(
F
_
K
L
C
I
C
P
0
3
t
i
B
1
w
e
l
S
_
)
2
:
3
(
6
6
V
3
1
.
s
t
i
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
)
1
:
2
(
6
6
V
3
k
a
e
w
=
0
1
;
l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
2
t
i
B
1
w
e
l
S
_
)
2
:
3
(
6
6
V
3
0
1
t
i
B
1
w
e
l
S
_
)
0
:
1
(
6
6
V
3
1
.
s
t
i
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
)
0
:
1
(
6
6
V
3
k
a
e
w
=
0
1
;
l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
0
t
i
B
0
w
e
l
S
_
)
0
:
1
(
6
6
V
3
0
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
1
w
e
l
S
F
E
R
1
.
s
t
i
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
F
E
R
k
a
e
w
=
0
1
;
l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
6
t
i
B
0
w
e
l
S
F
E
R
0
5
t
i
B
1
w
e
l
S
)
4
:
6
(
I
C
P
1
.
s
t
i
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
)
4
:
6
(
I
C
P
k
a
e
w
=
0
1
;
l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
4
t
i
B
0
w
e
l
S
)
4
:
6
(
I
C
P
0
3
t
i
B
)
2
:
3
(
I
C
P
1
w
e
l
S
1
.
s
t
i
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
)
2
:
3
(
I
C
P
k
a
e
w
=
0
1
;
l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
2
t
i
B
)
2
:
3
(
I
C
P
0
w
e
l
S
0
1
t
i
B
)
0
:
1
(
I
C
P
1
w
e
l
S
1
.
s
t
i
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
)
0
:
1
(
I
C
P
k
a
e
w
=
0
1
;
l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
0
t
i
B
)
0
:
1
(
I
C
P
0
w
e
l
S
0
t
i
B
e
m
a
N
D
W
P
n
o
i
t
p
i
r
c
s
e
D
7
t
i
B
d
e
v
r
e
s
e
R
X
d
e
v
r
e
s
e
R
6
t
i
B
d
e
v
r
e
s
e
R
X
5
t
i
B
d
e
v
r
e
s
e
R
1
4
t
i
B
d
e
v
r
e
s
e
R
0
3
t
i
B
1
w
e
l
S
z
H
M
8
4
1
.
s
t
i
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
z
H
M
8
4
k
k
a
e
w
=
0
1
;
l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
2
t
i
B
0
w
e
l
S
z
H
M
8
4
0
1
t
i
B
1
w
e
l
S
z
H
M
8
4
_
4
2
1
.
s
t
i
b
l
o
r
t
n
o
c
e
t
a
r
w
e
l
s
k
c
o
l
c
z
H
M
8
4
_
4
2
k
a
e
w
=
0
1
;
l
a
m
r
o
n
=
1
1
:
g
n
o
r
t
s
=
1
0
0
t
i
B
0
w
e
l
S
z
H
M
8
4
_
4
2
0
t
i
B
e
m
a
N
D
W
P
e
c
n
e
u
q
e
S
g
n
i
m
m
a
r
g
o
r
P
7
t
i
B
l
o
r
t
n
o
c
s
t
i
b
4
e
s
e
h
T
)
0
:
9
(
I
C
P
-
U
P
C
1
0
0 0 0
s
p
0
d
e
v
r
e
s
e
R
6
t
i
B
0
0
1 0 0
s
p
0
5
1
d
e
v
r
e
s
e
R
5
t
i
B
0
1
0 0 0
s
p
0
0
3
d
e
v
r
e
s
e
R
4
t
i
B
0
1
1 0 0
s
p
0
5
4
d
e
v
r
e
s
e
R
3
t
i
B
d
e
v
r
e
s
e
R
1
1
1 0
1
s
p
0
0
6
d
e
v
r
e
s
e
R
2
t
i
B
0
1
1 1 0
s
p
0
5
7
d
e
v
r
e
s
e
R
1
t
i
B
0
1
1 1 1
s
p
0
0
9
d
e
v
r
e
s
e
R
0
t
i
B
0
d
e
v
r
e
s
e
R
d
e
v
r
e
s
e
R
13
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0C to +70C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
V
IH
2
V
DD
+ 0.3
V
Input Low Voltage
V
IL
V
SS
- 0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
5
mA
Input Low Current
I
IL1
V
IN
= 0 V; Inputs with no pull-up
resistors
-5
mA
Input Low Current
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
mA
Operating Supply
Current
I
DD(op)
C
L
= 0 pF; Select @ 100MHz
203
260
mA
Power Down Supply
Current
I
DDPD
C
L
= 0 pF; With input address to Vdd or
GND
23
40
mA
Input frequency
F
i
V
DD
= 3.3 V;
11
14.31818
16
MHz
C
IN
Logic Inputs
5
pF
C
INX
X1 & X2 pins
27
45
pF
Clk Stabilization
1
T
STAB
From V
DD
= 3.3 V to 1% target Freq.
1
1.8
ms
T
SK3V66-PCI
V
T
= 1.5V/V
T
= 1.5 V
1.5
2.5
3.5
T
CPUT-3V66
V
T
= 50% /V
T
= 1.5 V
5.58
ns
1
Guaranteed by design, not 100% tested in production.
Input Capacitance
1
Skew
1
14
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Electrical Characteristics - CPUCLKT/C
T
A
= 0 - 70C; VDD=3.3V +/-5%; C
L
= 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Current Source Output
Impedance
Zo
Vo = Vx
3000
Output High Voltage
V
OH
1.08
1.2
V
Output High Current
I
OH
-14.81
mA
Rise Time
1
t
r
V
OL
= 0.175V, V
OH
= 0.525 V
175
328
700
ps
Fall Time
1
t
f
V
OH
= 0.525 V, V
OL
= 0.175 V
175
312
700
ns
Duty Cycle
1
d
t
V
T
= 50%
45
50
55
%
Differential Crossover
Voltage
1
Vx
Note 3
280
290
430
mV
Skew
1
t
sk
V
T
= 50%
35
100
ps
Jitter, Cycle-to-cycle1
tjcyc-cyc
V
T
= V
x
100
150
ps
1
Guaranteed by design, not 100% tested in production.
V
R
= 475
+1%; IREF =
2.32mA; I
OH
= 6*IREF
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3V +/-5%; CL= 10- 30pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Frequency
F01
33.33
MHz
Output Impedance
R
DSN1
VO = VDD*(0.5)
12
55
Output High Voltage
V
OH1
I
OH
= -1mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= -1mA
0.55
V
V
OH
=1.0V
-33
V
OH
=3.135V
-33
V
OL
= 1.95 V
30
V
OL
= 0.4V
38
Rise Time
tr1
V
OL
= 0.4V, V
OH
=2.4V
0.5
1.94
2
ns
Fall Time
tf1
V
OH
= 2.4V, V
OL
= 0.4V
0.5
1.78
2
ns
Duty Cycle
dt1
V
T
= 1.5V
45
51.9
55
%
Skew
tsk1
V
T
= 1.5V
133
500
ps
Jitter
tjcyc-cyc
V
T
= 1.5V
225
250
ps
1
Guaranteed by design,not 100% tested in production
Output High Current
I
OH1
mA
Output Low Current
I
OL1
mA
15
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Electrical Characteristics - 3V66
T
A
= 0 - 70C; VDD=3.3V +/-5%; C
L
= 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Output Frequency
F
O1
1
66.66
MHz
Output Impedance
R
DSP1
1
VO = VDD*(0.5)
12
55
Output High Voltage
V
OH1
I
OH
= -1mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= -1mA
0.55
V
V
OH
=1.0V
-33
V
OH
=3.135V
-33
V
OL
= 1.95 V
30
V
OL
= 0.4V
38
Rise Time
t
r1
V
OL
= 0.4V, V
OH
=2.4V
0.5
1.94
2
ns
Fall Time
t
f1
V
OH
= 2.4V, V
OL
= 0.4V
0.5
1.78
2
ns
Duty Cycle
d
t1
V
T
= 1.5V
45
50.7
55
%
Skew
t
f1
V
T
= 1.5V
82
500
ps
Jitter
t
jcyc-cyc1
V
T
= 1.5V
45
245
250
ps
1
Guaranteed by design,not 100% tested in production
Output High Current
I
OH1
mA
Output Low Current
I
OL1
mA
Electrical Characteristics - 24, 48MHz
TA = 0 - 70C; VDD = 3.3V +/-5%; CL= 10-30pF (unlessotherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Frequency
F
O
1
VO = VDD*(0.5)
24, 48
MHz
Output Impedance
R
DSN1
1
VO = VDD*(0.5)
12
55
Output High Voltage
V
OH1
I
OH
= -1mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= -1mA
0.55
V
V
OH
=1.0V
-29
V
OH
=3.135V
-23
V
OL
= 1.95 V
29
V
OL
= 0.4V
27
Rise Time
t
r1
1
V
OL
= 0.4V, V
OH
=2.4V
1
1.25
2
ns
Fall Time
t
f1
1
V
OH
= 2.4V, V
OL
= 0.4V
1
1.25
2
ns
Duty Cycle
d
t1
1
V
T
= 1.5V
45
52
55
%
Jitter
t
jcyc-cyc
1
V
T
= 1.5V
150
350
ps
1
Guaranteed by design,not 100% tested in production
Output High Current
I
OH1
mA
Output Low Current
I
OL1
mA
16
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Electrical Characteristics - REF
T
A
= 0 - 70C; V
DD
= 3.3 V , +/-5%; C
L
= 10 - 20 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Output Frequency
F
O1
1
14.318
MHz
Output Impedance
R
DSP1
1
V
O
= V
DD
*(0.5)
20
60
Output High Voltage
V
OH1
I
OH
= -1mA
2.4
V
Output Low Voltage
V
OL1
I
OL
= -1mA
0.55
V
V
OH
=1.0V
-33
mA
V
OH
=3.135V
-33
V
OL
= 1.95 V
30
mA
V
OL
= 0.4V
38
Rise Time
t
r1
V
OL
= 0.4V, Voh =2.4V
0.5
1.71
2
ns
Fall Time
t
f1
V
OH
= 2.4V, V
OL
= 0.4V
0.5
1.68
2
ns
Duty Cycle
d
t1
V
T
= 1.5V
45
54
55
%
Jitter
t
jcyc-cyc1
V
T
= 1.5V
450
500
ps
1
Guaranteed by design,not 100% tested in production
Output High Current
I
OH1
Output Low Current
I
OL1
17
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
Fig. 1
Shared Pin Operation -
Input/Output Pins
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Clock trace to load
Series Term. Res.
Programming
Header
Via to Gnd
Device
Pad
2K
W
8.2K
W
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
18
Integrated
Circuit
Systems, Inc.
ICS950208
0464B--08/04/03
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard
skew described below as Tpci.
Un-Buffered Mode 3V66 & PCI Phase Relationship
3V66
PCICLK_F and PCICLK
Tpci
Integrated
Circuit
Systems, Inc.
ICS950208
19
0464B--08/04/03
Ordering Information
ICS950208yFT
Designation for tape and reel packaging
Package Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - T
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
h x 45
h x 45
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
- C -
b
.10 (.004) C
.10 (.004) C
c
L
300 mil SSOP Package
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.03
10.68
.395
.420
E1
7.40
7.60
.291
.299
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
0
8
0
8
MIN
MAX
MIN
MAX
48
15.75
16.00
.620
.630
10-0034
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS
COMMON DIMENSIONS
SEE VARIATIONS
SEE VARIATIONS
0.635 BASIC
0.025 BASIC
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
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