Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Block Diagram
950211 Rev A 01/23/02
Pin Configuration
Recommended Application:
CK-408 clock with driven mode only for Brookdale chipset with P4
processor.
Output Features:
3 - Pairs of differential CPU clocks (differential current mode)
5 - 3V66 @ 3.3V
10 - PCI @ 3.3V
2 - 48MHz @ 3.3V fixed
1 - REF @ 3.3V, 14.318MHz
1 - VCH/3V66 @ 3.3V, 48 MHz or 66.6 MHz
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/write operations.
Uses external 14.318MHz crystal.
Key Specifications:
CPU Output Jitter <150ps
3V66 Output Jitter <250ps
CPU Output Skew <100ps
Programmable Timing Control Hub for P4
1. These outputs have 2X drive strength.
* Internal Pull-up resistor of 120K to VDD
** these inputs have 120K internal pull-down
to GND
56-Pin 300-mil SSOP
Power Groups
VDDA = Analog Core PLL
VDDREF = REF, Xtal
AVDD48 = 48MHz
Frequency Table
For additional frequency selections please refer to Byte 0.
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
*WDEN/PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_2
3V66_3
3V66_4
3V66_5
#
VDDA
GND
*Vtt_PWRGD#
1
1
1
*PD
REF
FS1
FS0
CPU_STOP#*
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTSEL0*
I REF
GND
FS2
48MHz_USB/FS3**
48MHz_DOT
VDD48
GND
3V66_1/VCH_CLK/FS4**
PCI_STOP#*
3V66_0
VDD3V66
GND
SCLK
SDATA
1
ICS950211
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PLL2
PLL1
Spread
Spectrum
48MHz_USB
PCICLK (6:0)
3V66 (5:2, 0)
48MHz_DOT
3V66_0/VCH_CLK
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
3V66
DIVDER
WDEN
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
SDATA
SCLK
Vtt_PWRGD#
FS (4:0)
I REF
Control
Logic
Config.
Reg.
REF
3
3
7
5
3
CPUCLKT (2:0)
CPUCLKC (2:0)
PCICLK_F (2:0)
Stop
Stop
4
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1
3
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change
without notice.
2
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Pin Description
The ICS950211 is a single chip clock solution for desktop designs using the Intel Brookdale chipset with PC133 or DDR
memory. It provides all necessary clock signals for such a system.
The ICS950211 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
General Description
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Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Maximum Allowed Current
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Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
*See notes on the following page
.
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byt
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
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RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
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P
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Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byt
e
ACK
ACK
5
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS950211
Preliminary Product Preview
Byte 0: Functionality and frequency select register (Default=0)
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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