Integrated
Circuit
Systems, Inc.
ICS950905
Advance Information
Block Diagram
950905 Rev - 11/26/01
Pin Configuration
Recommended Application:
VIA P4X266 chipset with PC133 or DDR memory.
Output Features:
2 - Pair of differential CPU clocks @ 3.3V
1 - Pair of differential push pull CPU_CS clocks @ 2.5V
3 - AGP @ 3.3V
9 - PCI @ 3.3V
1- IOAPIC @ 2.5V
1 - 48MHz @ 3.3V fixed
1 - 24_48MHz @ 3.3V
1 - REF @ 3.3V, 14.318MHz
Features/Benefits:
Programmable output frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system
if system malfunctions.
Programmable watch dog safe frequency.
Support I
2
C Index read/write and block read/write
operations.
For DDR and or PC133 SDRAM system use ICS93718
as the memory buffer.
Uses external 14.318MHz crystal.
Key Specifications:
CPU_CS - CPU0: <250ps
CPU_CS - AGP: <250ps
PCI - PCI: <500ps
CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Programmable Timing Control HubTM for P4TM
1. These outputs have 2X drive strength.
* These inputs have a internal Pull-up resistor
of 120K to VDD
** These inputs have a internal pull-down to GND
48-Pin 300-mil SSOP
Frequency Table
I REF
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
IOAPIC
PCICLK (7:0)
AGPCLK (2:0)
RESET#
PCICLK_F
3
X1
X2
XTAL
OSC
CPU
DIVDER
CPU
DIVDER
IOAPIC
DIVDER
PCI
DIVDER
AGP
DIVDER
Stop
Stop
Stop
SEL24_48
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
CPU_STOP#
MULTI_SEL
Vtt_PWRGD#
Control
Logic
Config.
Reg.
/ 2
REF0
CPUCLKT_(1:0)
CPUCLKC_(1:0)
CPUCLK_PPT
CPUCLK_PPC
WDEN
WDTB
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ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
1
**SEL24_48/REF0
VDDREF
GND
X1
X2
VDD48
*FS3/48MHz
*FS2/24_48MHz
GND
*FS0/PCICLK_F
**FS1/PCICLK0
*MULTI_SEL/PCICLK1
GND
PCICLK2
PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
*PD#
AGPCLK0
VDDAGP
*WDTB/
**WDEN/
VDDLAPIC
GND
N/C
IOAPIC
GND
VDDCPU_PP (2.5V)
CPUCLK_PPT
CPUCLK_PPC
CPUCLKT_0
CPUCLKC_0
VDDCPU (3.3V)
I REF
GND
CPUCLKT_1
CPUCLKC_1
Vtt_PWRGD#
CPU_STOP#*
PCI_STOP#*
RESET#
SDATA
SCLK
AGPCLK2
AGPCLK1
GND
ICS950905
1
2
3
4
5
6
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33
32
31
30
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28
27
26
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2
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS950905
Advance Information
Pin Description
The ICS950905 is a single chip clock solution for desktop designs using the VIA P4X266 chipset with PC133 or DDR memory.
with PC133 or DDR memory. When used with a fanout buffer such as the ICS93712, ICS93715 or the ICS93718 provides all
the necessary clock signals for such a system.
The ICS950905 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
General Description
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3
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS950905
Advance Information
General I
2
C serial interface information
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
*See notes on the following page
.
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byt
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byt
e
ACK
ACK
4
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS950905
Advance Information
Byte 0: Functionality and frequency select register (Default=0)
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
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b
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t
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1
0
5
Third party brands and names are the property of their respective owners.
Integrated
Circuit
Systems, Inc.
ICS950905
Advance Information
Byte 1: CPU Active/Inactive Register
(1 = enable, 0 = disable)
Byte 3: Active/Inactive Register
(1 = enable, 0 = disable)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Byte 4: Frequency Select Active/Inactive Register
(1 = enable, 0 = disable)
t
i
B
#
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7
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9
1
1
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(
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7
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(
4
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(
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2
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