Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
Pin Configuration
Recommended Application:
CK409 clock, Intel Yellow Cover part
Output Features:
3 - 0.7V current-mode differential CPU pairs
1 - 0.7V current-mode differential SRC pair
7 - PCI (33MHz)
3 - PCICLK_F, (33MHz) free-running
1 - USB, 48MHz
1 - DOT, 48MHz
2 - REF, 14.318MHz
4 - 3V66, 66.66MHz
1 - VCH/3V66, selectable 48MHz or 66MHz
Key Specifications:
CPU/SRC outputs cycle-cycle jitter < 125ps
3V66 outputs cycle-cycle jitter < 250ps
PCI outputs cycle-cycle jitter < 250ps
CPU outputs skew: < 100ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
Programmable Timing Control HubTM for Next Gen P
4
TM processor
Functionality
Features/Benefits:
Supports tight ppm accuracy clocks for Serial-ATA.
Supports spread spectrum modulation, 0 to -0.5%
down spread.
Supports CPU clks up to 400MHz in test mode.
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning.
Supports undriven differential CPU, SRC pair in PD#
and CPU_STOP# for power management.
56-pin SSOP & TSSOP
B6b5 FS_A FS_B
CPU
MHz
SRC
MHz
3V66
MHz
PCI
MHz
REF
MHz
U
SB/DOT
MHz
0
0
100
100/200 66.66
33.33 14.318
48.00
0
MID
Ref/N
0
Ref/N
1
Ref/N
2
Ref/N
3
Ref/N
4
Ref/N
5
0
1
200
100/200 66.66
33.33 14.318
48.00
1
0
133
100/200 66.66
33.33 14.318
48.00
1
1
166
100/200 66.66
33.33 14.318
48.00
1
MID
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
0
0
200
100/200 66.66
33.33 14.318
48.00
0
1
400
100/200 66.66
33.33 14.318
48.00
1
0
266
100/200 66.66
33.33 14.318
48.00
1
1
333
100/200 66.66
33.33 14.318
48.00
0
1
REF0
1
56 FS_B
REF1
2
55 VDDA
VDDREF
3
54 GNDA
X1
4
53 GND
X2
5
52 IREF
GND
6
51 FS_A
PCICLK_F0
7
50 CPU_STOP#
PCICLK_F1
8
49 PCI_STOP#
PCICLK_F2
9
48 VDDCPU
VDDPCI 10
47 CPUCLKT2
GND 11
46 CPUCLKC2
PCICLK0 12
45 GND
PCICLK1 13
44 CPUCLKT1
PCICLK2 14
43 CPUCLKC1
PCICLK3 15
42 VDDCPU
VDDPCI 16
41 CPUCLKT0
GND 17
40 CPUCLKC0
PCICLK4 18
39 GND
PCICLK5 19
38 SRCCLKT
PCICLK6 20
37 SRCCLKC
PD# 21
36 VDD
3V66_0 22
35 Vtt_PWRGD#
3V66_1 23
34 VDD48
VDD3V66 24
33 GND
GND 25
32 48MHz_DOT
3V66_2 26
31 48MHz_USB
3V66_3 27
30 SDATA
SCLK 28
29 3V66_4/VCH
ICS9526
01
2
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
REF0
OUT
14.318 MHz reference clock.
2
REF1
OUT
14.318 MHz reference clock.
3
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
4
X1
IN
Crystal input, Nominally 14.318MHz.
5
X2
OUT
Crystal output, Nominally 14.318MHz
6
GND
PWR
Ground pin.
7
PCICLK_F0
OUT
Free running PCI clock not affected by PCI_STOP# .
8
PCICLK_F1
OUT
Free running PCI clock not affected by PCI_STOP# .
9
PCICLK_F2
OUT
Free running PCI clock not affected by PCI_STOP# .
10
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
11
GND
PWR
Ground pin.
12
PCICLK0
OUT
PCI clock output.
13
PCICLK1
OUT
PCI clock output.
14
PCICLK2
OUT
PCI clock output.
15
PCICLK3
OUT
PCI clock output.
16
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
17
GND
PWR
Ground pin.
18
PCICLK4
OUT
PCI clock output.
19
PCICLK5
OUT
PCI clock output.
20
PCICLK6
OUT
PCI clock output.
21
PD#
IN
Asynchronous active low input pin used to power down the device into a
low power state. The internal clocks are disabled and the VCO and the
crystal are stopped. The latency of the power down will not be greater
than 1.8ms. Internal pull-up of 150K nominal.
22
3V66_0
OUT
3.3V 66.66MHz clock output
23
3V66_1
OUT
3.3V 66.66MHz clock output
24
VDD3V66
PWR
Power pin for the 3V66 clocks.
25
GND
PWR
Ground pin.
26
3V66_2
OUT
3.3V 66.66MHz clock output
27
3V66_3
OUT
3.3V 66.66MHz clock output
28
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
3
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
29
3V66_4/VCH
OUT
66.66MHz clock output for AGP support. AGP-PCI should be aligned
with a skew window tolerance of 500ps.
VCH is 48MHz clock output for video controller hub.
30
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
31
48MHz_USB
OUT
48MHz clock output.
32
48MHz_DOT
OUT
48MHz clock output.
33
GND
PWR
Ground pin.
34
VDD48
PWR
Power pin for the 48MHz output.3.3V
35
Vtt_PWRGD#
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
36
VDD
PWR
Power supply for SRC clocks, nominal 3.3V
37
SRCCLKC
OUT
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
38
SRCCLKT
OUT
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
39
GND
PWR
Ground pin.
40
CPUCLKC0
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
41
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
42
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
43
CPUCLKC1
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
44
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
45
GND
PWR
Ground pin.
46
CPUCLKC2
OUT
Complimentary clock of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
47
CPUCLKT2
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
48
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
49
PCI_STOP#
IN
Stops all PCICLKs and SRC pair besides the PCICLK_F clocks at logic
0 level, when input low. PCI and SRC clocks can be set to
Free_Running through I2C. Internal pull-up of 150K nominal.
50
CPU_STOP#
IN
Stops all CPUCLK besides the free running clocks. Internal pull-up of
150K nominal
51
FS_A
IN
Frequency select pin, see Frequency table for functionality
52
IREF
OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
53
GND
PWR
Ground pin.
54
GNDA
PWR
Ground pin for core.
55
VDDA
PWR
3.3V power for the PLL core.
56
FS_B
IN
Frequency select pin, see Frequency table for functionality
4
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
ICS952601 follows Intel CK409 Yellow Cover specification. This clock synthesizer provides a single chip solution for next
generation P4 Intel processors and Intel chipsets. ICS952601 is driven with a 14.318MHz crystal. It generates CPU outputs up
to 200MHz. It also provides a tight ppm accuracy output for Serial ATA support.
General Description
Block Diagram
I REF
PLL2
Frequency
Dividers
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
STOP
Logic
48MHz, USB, DOT, VCH
X1
X2
XTAL
SDATA
SCLK
CPU_STOP#
PCI_STOP#
Vtt_PWRGD#
PD#
FS_A
FS_B
Control
Logic
REF (1:0)
CPUCLKT (2:0)
CPUCLKC (2:0)
SRCCLKT0
SRCCLKC0
3V66(4:0)
PCICLK (6:0)
PCICLKF (2:0)
Power Groups
VDD
GND
3
6
Xtal, Ref
24
25
3V66 [0:3]
10,16
11,17
PCICLK outputs
36
39
SRCCLK outputs
55
54
Master clock, CPU Analog
34
33
48MHz, PLL, SCLK, SDATA
N/A
53
IREF
48, 42
45
CPUCLK clocks
Description
Pin Number
5
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
Absolute Max
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
V
DD
+ 0.5V
V
VDD_In
3.3V Logic Input Supply Voltage
GND - 0.5
V
DD
+ 0.5V
V
Ts
Storage Temperature
-65
150
C
Tambient Ambient
Operating Temp
0
70
C
Tcase Case
Temperature
115
C
ESD prot
Input ESD protection human body model
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
V
IH
3.3 V +/-5%
2
V
DD
+ 0.3
V
Input MID Voltage
V
MID
3.3 V +/-5%
1
1.8
V
Input Low Voltage
V
IL
3.3 V +/-5%
V
SS
- 0.3
0.8
V
Input High Current
I
IH
V
IN
= V
DD
-5
5
uA
I
IL1
V
IN
= 0 V; Inputs with no pull-up
resistors
-5
uA
I
IL2
V
IN
= 0 V; Inputs with pull-up
resistors
-200
uA
Operating Supply Current
I
DD3.3OP
Full Active, C
L
= Full load;
258
350
mA
all diff pairs driven
29
35
mA
all differential pairs tri-stated
0.3
12
mA
Input Frequency
3
F
i
V
DD
= 3.3 V
14.31818
MHz
3
Pin Inductance
1
L
pin
7
nH
1
C
IN
Logic Inputs
5
pF
1
C
OUT
Output pin capacitance
6
pF
1
C
INX
X1 & X2 pins
5
pF
1
Clk Stabilization
1,2
T
STAB
From V
DD
Power-Up or de-
assertion of PD# to 1st clock
1.8
ms
1,2
Modulation Frequency
Triangular Modulation
30
33
kHz
1
Tdrive_SRC
SRC output enable after
PCI_Stop# de-assertion
15
ns
1
Tdrive_PD#
CPU output enable after
PD# de-assertion
300
us
1
Tfall_Pd#
PD# fall time of
5
ns
1
Trise_Pd#
PD# rise time of
5
ns
2
Tdrive_CPU_Stop#
CPU output enable after
CPU_Stop# de-assertion
10
us
1
Tfall_CPU_Stop#
PD# fall time of
5
ns
1
Trise_CPU_Stop#
PD# rise time of
5
ns
2
SMBus Voltage
V
DD
2.7
5.5
V
1
Low-level Output Voltage
V
OL
@ I
PULLUP
0.4
V
1
Current sinking at V
OL
= 0.4 V
I
PULLUP
4
mA
1
SCLK/SDATA
Clock/Data Rise Time
3
T
RI2C
(Max VIL - 0.15) to (Min VIH + 0.15)
1000
ns
1
SCLK/SDATA
Clock/Data Fall Time
3
T
FI2C
(Min VIH + 0.15) to (Max VIL - 0.15)
300
ns
1
1
Guaranteed by design, not 100% tested in production.
2
See timing diagrams for timing requirements.
I
DD3.3PD
3
Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet
ppm frequency accuracy on PLL outputs.
Input Capacitance
1
Input Low Current
Powerdown Current
6
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
Electrical Characteristics - CPU & SRC 0.7V Current Mode Differential Pair
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
=2pF
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Current Source Output
Impedance
Zo
1
V
O
= V
x
3000
1
Voltage High
VHigh
660
770
850
1
Voltage Low
VLow
-150
5
150
1
Max Voltage
Vovs
756
1150
1
Min Voltage
Vuds
-300
-7
1
Crossing Voltage (abs) Vcross(abs)
250
350
550
mV
1
Crossing Voltage (var)
d-Vcross
Variation of crossing over all
edges
12
140
mV
1
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
1,2
200MHz nominal
4.9985
5.0000
5.0015
ns
2
200MHz spread
4.9985
5.0266
ns
2
166.66MHz nominal
5.9982
6.0000
6.0018
ns
2
166.66MHz spread
5.9982
6.0320
ns
2
133.33MHz nominal
7.4978
7.5000
7.5023
ns
2
133.33MHz spread
7.4978
5.4000
ns
2
100.00MHz nominal
9.9970
10.0000 10.0030
ns
2
100.00MHz spread
9.9970
10.0533
ns
2
200MHz nominal
4.8735
ns
1,2
166.66MHz nominal/spread
5.8732
ns
1,2
133.33MHz nominal/spread
7.3728
ns
1,2
100.00MHz nominal/spread
9.8720
ns
1,2
Rise Time
t
r
V
OL
= 0.175V, V
OH
= 0.525V
175
332
700
ps
1
Fall Time
t
f
V
OH
= 0.525V V
OL
= 0.175V
175
344
700
ps
1
Rise Time Variation
d-t
r
30
125
ps
1
Fall Time Variation
d-t
f
30
125
ps
1
Duty Cycle
d
t3
Measurement from differential
wavefrom
45
49
55
%
1
Skew
t
sk3
V
T
= 50%
8
100
ps
1
Jitter, Cycle to cycle
t
jcyc-cyc
Measurement from differential
wavefrom
37
125
ps
1
1
Guaranteed by design, not 100% tested in production.
SRC clock outputs run at only 100MHz or 200MHz, specs for 133.33 and 166.66 do not apply to SRC clock pair.
Statistical measurement on single
ended signal using oscilloscope
math function.
mV
Measurement on single ended
signal using absolute value.
mV
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
Tperiod
Average period
Absolute min period
T
absmin
7
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
Electrical Characteristics - 3V66 Mode: 3V66 [4:0]
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
1,2
66.66MHz output nominal
14.9955
15
15.0045
ns
2
66.66MHz output spread
14.9955
15.0799
ns
2
Output High Voltage
V
OH
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 1 mA
0.55
V
V
OH
@ MIN = 1.0 V
-33
mA
V
OH
@ MAX = 3.135 V
-33
mA
V
OL
@ MIN = 1.95 V
30
mA
V
OL
@ MAX = 0.4 V
38
mA
Edge Rate
Rising edge rate
1
4
V/ns
1
Edge Rate
Falling edge rate
1
4
V/ns
1
Rise Time
t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V
0.5
1.92
2
ns
1
Fall Time
t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V
0.5
1.97
2
ns
1
Duty Cycle
d
t1
V
T
= 1.5 V
45
53.1
55
%
1
Skew
t
sk1
V
T
= 1.5 V
38
250
ps
1
Jitter
t
jcyc-cyc
V
T
= 1.5 V 3V66
139
250
ps
1
1
Guaranteed by design, not 100% tested in production.
Clock period
T
period
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is at
14.31818MHz
Output High Current
I
OH
Output Low Current
I
OL
Electrical Characteristics - PCICLK/PCICLK_F
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10-30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
Long Accuracy
ppm
see Tperiod min-max values
-300
300
ppm
1,2
33.33MHz output nominal
29.9910
30
30.0090
ns
2
33.33MHz output spread
29.9910
30.1598
ns
2
Output High Voltage
V
OH
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 1 mA
0.55
V
V
OH
@MIN = 1.0 V
-33
mA
V
OH
@ MAX = 3.135 V
-33
mA
V
OL
@ MIN = 1.95 V
30
mA
V
OL
@ MAX = 0.4 V
38
mA
Edge Rate
Rising edge rate
1
4
V/ns
1
Edge Rate
Falling edge rate
1
4
V/ns
1
Rise Time
t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V
0.5
1.92
2
ns
1
Fall Time
t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V
0.5
1.9
2
ns
1
Duty Cycle
d
t1
V
T
= 1.5 V
45
51.4
55
%
1
Skew
t
sk1
V
T
= 1.5 V
18
500
ps
1
Jitter
t
jcyc-cyc
V
T
= 1.5 V 3V66
92
250
ps
1
1
Guaranteed by design, not 100% tested in production.
Clock period
T
period
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is
at 14.31818MHz
Output High Current
I
OH
Output Low Current
I
OL
8
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Notes
Long Accuracy
ppm
see Tperiod min-max
values
-200
200
ppm
1,2
Clock period
T
period
66.66MHz output nominal 20.8257
20.8340
ns
2
Output High Voltage
V
OH
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 1 mA
0.55
V
V
OH
@ MIN = 1.0 V
-33
mA
V
OH
@ MAX = 3.135 V
-33
mA
V
OL
@ MIN = 1.95 V
30
mA
V
OL
@ MAX = 0.4 V
38
mA
Edge Rate
Rising edge rate
2
4
V/ns
1
Edge Rate
Falling edge rate
2
4
V/ns
1
Rise Time
t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V
0.5
0.71
1
ns
1
Fall Time
t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V
0.5
0.77
1
ns
1
Duty Cycle
d
t1
V
T
= 1.5 V
45
49
55
%
1
Long Term Jitter
125us period jitter
(8kHz frequency
modulation amplitude)
0.7
2
ns
1
1
Guaranteed by design, not 100% tested in production.
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 5-10 pF (unless otherwise specified)
Electrical Characteristics - 48MHz DOT Clock
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref
output is at 14.31818MHz
Output High Current
I
OH
Output Low Current
I
OL
Electrical Characteristics - VCH, 48MHz, USB
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS Notes
Long Accuracy
ppm
see Tperiod min-max values
-200
200
ppm
1,2
Clock period
T
period
66.66MHz output nominal
20.8257
20.8340
ns
2
Output High Voltage
V
OH
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 1 mA
0.55
V
V
OH
@ MIN = 1.0 V
-33
mA
V
OH
@ MAX = 3.135 V
-33
mA
V
OL
@MIN = 1.95 V
30
mA
V
OL
@ MAX = 0.4 V
38
mA
Edge Rate
Rising edge rate
1
2
V/ns
1
Edge Rate
Falling edge rate
1
2
V/ns
1
Rise Time
t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V
1
1.43
2
ns
1
Fall Time
t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V
1
1.33
2
ns
1
Duty Cycle
d
t1
V
T
= 1.5 V
45
48
55
%
1
Long Term Jitter
125us period jitter
(8kHz frequency modulation
amplitude)
0.7
6
ns
1
1
Guaranteed by design, not 100% tested in production.
Output Low Current
I
OL
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that Ref output is
at 14.31818MHz
Output High Current
I
OH
9
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
Electrical Characteristics - REF-14.318MHz
T
A
= 0 - 70C; V
DD
= 3.3 V +/-5%; C
L
= 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Long Accuracy
ppm
1
see Tperiod min-max values
-300
300
ppm
Clock period
T
period
14.318MHz output nominal
69.8270
69.8550
ns
Output High Voltage
V
OH
1
I
OH
= -1 mA
2.4
V
Output Low Voltage
V
OL
1
I
OL
= 1 mA
0.4
V
Output High Current
I
OH
1
V
OH
@MIN = 1.0 V, V
OH
@MAX = 3.135 V
-29
-23
mA
Output Low Current
I
OL
1
V
OL
@MIN = 1.95 V, V
OL
@MAX = 0.4 V
29
27
mA
Rise Time
t
r1
1
V
OL
= 0.4 V, V
OH
= 2.4 V
1
1.92
2
ns
Fall Time
t
f1
1
V
OH
= 2.4 V, V
OL
= 0.4 V
1
1.92
2
ns
Skew
t
sk1
1
V
T
= 1.5 V
26
500
ps
Duty Cycle
d
t1
1
V
T
= 1.5 V
45
53.4
55
%
Jitter
t
jcyc-cyc
1
V
T
= 1.5 V
284
1000
ps
1
Guaranteed by design, not 100% tested in production.
Group to Group Skews at Common Transition Edges
GROUP
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
200MHZ CPU to
3V66
1
S
CPU200-3V66
3V66 (4:0) leads 200MHZ
CPU
-2.1
-1.6
-1.1
ns
3V66 to PCI
S
3V66-PCI
3V66 (4:0) leads 33MHz PCI
1.50
2.59
3.50
ns
DOT-USB
S
DOT_USB
180 degrees out of phase
0.00
1.00
ns
DOT-VCH
S
DOT_VCH
in phase
0.00
1.00
ns
1. 3V66 MHz C
L
= 0pf, Rseries = 33 ohm. CPU CL = 2 pf, Rseries = 33 ohm, Rshunt = 49.9 ohms.
Measured at the pins of the 952601.
10
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
General I
2
C serial interface information for the ICS952601
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
P
stoP bit
X Byt
e
Index Block Write Operation
Slave Address D2
(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3
(H)
Index Block Read Operation
Slave Address D2
(H)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byt
e
ACK
ACK
11
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
I
2
C Table: Read-Back Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
RESERVED
RESERVED
-
X
Bit 6
RESERVED
RESERVED
-
X
Bit 5
RESERVED
RESERVED
-
X
Bit 4
RESERVED
RESERVED
-
X
Bit 3
PCI_STOP#
PCI STOP# Read
Back
R
X
Bit 2
CPU_STOP#
CPU STOP Read
Back
R
X
Bit 1
FSB
Freq Select 1 Read
Back
R
X
Bit 0
FSA
Freq Select 0 Read
Back
R
X
I
2
C Table: Spreading and Device Behavior Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
SRC/SRC#
SRC Free-Running
Control
RW
FREE-RUN
STOPPABLE
0
Bit 6
SRC Output Control
RW
Disable
Enable
1
Bit 5
CPUT2/CPUC2
RW
FREE-RUN
STOPPABLE
1
Bit 4
CPUT1/CPUC1
RW
FREE-RUN
STOPPABLE
1
Bit 3
CPUT0/CPUC0
RW
FREE-RUN
STOPPABLE
1
Bit 2
CPUT2/CPUC2
Output Control
RW
Disable
Enable
1
Bit 1
CPUT1/CPUC1
Output Control
RW
Disable
Enable
1
Bit 0
CPUT0/CPUC0
Output Enable
RW
Disable
Enable
1
I
2
C Table: Output Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
SRC_PD#
Drive Mode
0: Driven in PD#
RW
Driven
Hi-Z
0
Bit 6
SRC_Stop#
Drive Mode
0: Driven in
PCI_Stop#
RW
Driven
Hi-Z
0
Bit 5
CPUT2_PD# Drive Mode
RW
Driven
Hi-Z
0
Bit 4
CPUT1_PD# Drive Mode
RW
Driven
Hi-Z
0
Bit 3
CPUT0_PD# Drive Mode
RW
Driven
Hi-Z
0
Bit 2
CPUT2_Stop Drive Mode
RW
Driven
Hi-Z
0
Bit 1
CPUT1_Stop Drive Mode
RW
Driven
Hi-Z
0
Bit 0
CPUT0_Stop Drive Mode
RW
Driven
Hi-Z
0
RESERVED
0:driven when
stopped
1: Tri-stated
0:driven in PD#
1: Tri-stated
-
READBACK
READBACK of CPU(2:0)
Frequency
READBACK
RESERVED
RESERVED
-
RESERVED
-
-
-
Byte 0
-
-
-
Byte 1
37,38
37,38
46,47
43,44
40,41
Byte 2
37,38
37,38
CPU FREE-
RUNNING
CONTROL
43,44
40,41
46,47
46,47
43,44
40,41
46,47
43,44
40,41
12
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
I
2
C Table: Output Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
PCI_Stop#
PCI_Stop# Control
0:all stoppable PCI
and SRC are
stopped
RW
Enable
Disable
1
Bit 6
PCICLK6
Output Control
RW
Disable
Enable
1
Bit 5
PCICLK5
Output Control
RW
Disable
Enable
1
Bit 4
PCICLK4
Output Control
RW
Disable
Enable
1
Bit 3
PCICLK3
Output Control
RW
Disable
Enable
1
Bit 2
PCICLK2
Output Control
RW
Disable
Enable
1
Bit 1
PCICLK1
Output Control
RW
Disable
Enable
1
Bit 0
PCICLK0
Output Control
RW
Disable
Enable
1
I
2
C Table: Output Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
48MHz_USB
2x output drive
0=2x drive
RW
2x drive
normal
0
Bit 6
48MHz_USB
Output Control
RW
Disable
Enable
1
Bit 5
PCIF2
RW
FREE-RUN
STOPPABLE
0
Bit 4
PCIF1
RW
FREE-RUN
STOPPABLE
0
Bit 3
PCIF0
RW
FREE-RUN
STOPPABLE
0
Bit 2
PCICLK_F2
Output Control
RW
Disable
Enable
1
Bit 1
PCICLK_F1
Output Control
RW
Disable
Enable
1
Bit 0
PCICLK_F0
Output Control
RW
Disable
Enable
1
I
2
C Table: Output Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
48MHZ_DOT
Output Control
RW
Disable
Enable
1
Bit 6
RESERVED
RESERVED
`
-
-
0
Bit 5
3V66_4/VCH
Select
Output Select
RW
3V66
VCH
0
Bit 4
3V66_4/VCH
Output Control
RW
Disable
Enable
1
Bit 3
3V66_3
Output Control
RW
Disable
Enable
1
Bit 2
3V66_2
Output Control
RW
Disable
Enable
1
Bit 1
3V66_1
Output Control
RW
Disable
Enable
1
Bit 0
3V66_0
Output Control
RW
Disable
Enable
1
Byte 4
31
31
9
8
PCI FREE-RUN
NING CONTROL
7
Byte 3
7,8,9,12,13,14,15,
18,19,20,37,38,
20
19
18
15
14
-
29
29
27
26
23
13
12
Byte 5
32
9
8
7
22
13
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
I
2
C Table: Output Control and Fix Frequency Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
Test Clock Mode
Test Clock Mode
-
Disable
Enable
0
Bit 6
RESERVED
-
-
-
-
0
Bit 5
RESERVED
FS_A and FS_B
Operation
-
Normal
Test Mode
0
Bit 4
RESERVED
SRC Frequency
Select
-
100MHz
200MHz
0
Bit 3
RESERVED
-
-
-
-
0
Bit 2
Spread Spectrum Mode
Spread OFF
Spread
ON
0
Bit 1
REF1
Output Control
RW
Disable
Enable
1
Bit 0
REF0
Output Control
RW
Disable
Enable
1
I
2
C Table: Vendor & Revision ID Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
RID3
R
-
-
X
Bit 6
RID2
R
-
-
X
Bit 5
RID1
R
-
-
X
Bit 4
RID0
R
-
-
X
Bit 3
VID3
R
-
-
0
Bit 2
VID2
R
-
-
0
Bit 1
VID1
R
-
-
0
Bit 0
VID0
R
-
-
1
1,2,7,8,9,12,13,14,1
5,18,19,20,22,23,26,
27,29,31,32,37,38,4
0,41,43,44,46,47
-
40,41,43,44,46,47
Byte 6
2
1
37,38
7,8,9,12,13,14,15,18
,19,20,22,23,26,27,2
9,31,32,37,38,40,41,
43,44,46,47
Byte 7
-
REVISION ID
-
-
-
-
VENDOR ID
-
-
-
14
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF (2:0) and SRC clocks can be set to
be free-running through I2C programming. Outputs set to be free-running will ignore both the PCI_STOP pin and the
PCI_STOP register bit.
PCI Stop Functionality
#
P
O
T
S
_
I
C
P
U
P
C
#
U
P
C
C
R
S
#
C
R
S
6
6
V
3
I
C
P
/
F
I
C
P
T
O
D
/
B
S
U
F
E
R
e
t
o
N
1
l
a
m
r
o
N
l
a
m
r
o
N
l
a
m
r
o
N
l
a
m
r
o
N
z
H
M
6
6
z
H
M
3
3
z
H
M
8
4
z
H
M
8
1
3
.
4
1
0
l
a
m
r
o
N
l
a
m
r
o
N
6
*
f
e
r
I
t
a
o
l
F
r
o
w
o
L
z
H
M
6
6
w
o
L
z
H
M
8
4
z
H
M
8
1
3
.
4
1
The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all
PCI[6:0] and stoppable PCIF[2:0] clocks will latch low on their next high to low transition. After the PCI clocks are latched low,
the SRC clock, (if set to stoppable) will latch high at Iref * 6 (or tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and
the SRC# will latch low as shown below.
PCI_STOP#
Tsu
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# Assertion (transition from '1' to '0')
The de-assertion of the PCI_Stop# signal is to be sampled on the rising edge of the PCIF free running clock domain. After
detecting PCI_Stop# de-assertion, all PCI[6:0], stoppable PCIF[2:0] and stoppable SRC clocks will resume in a glitch free
manner.
PCI_STOP#
Tsu
Tdrive_SRC
PCIF[2:0] 33MHz
PCI[6:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# - De-assertion
15
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.
CPU_STOP# Functionality
#
P
O
T
S
_
U
P
C
U
P
C
#
U
P
C
C
R
S
#
C
R
S
6
6
V
3
I
C
P
/
F
I
C
P
T
O
D
/
B
S
U
F
E
R
e
t
o
N
1
l
a
m
r
o
N
l
a
m
r
o
N
l
a
m
r
o
N
l
a
m
r
o
N
z
H
M
6
6
z
H
M
3
3
z
H
M
8
4
z
H
M
8
1
3
.
4
1
0
r
o
6
*
f
e
r
I
t
a
o
l
F
w
o
L
l
a
m
r
o
N
l
a
m
r
o
N
z
H
M
6
6
z
H
M
3
3
z
H
M
8
4
z
H
M
8
1
3
.
4
1
Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the I2C
CPU_STOP tri-state bit corresponding to the CPU output of interest is programmed to a '0', CPU output will stop CPU_True
= HIGH and CPU_Complement = LOW. When the I2C CPU_Stop tri-state bit corresponding to the CPU output of interest is
programmed to a '1', CPU outputs will be tri-stated.
CPU_STOP#
CPU
CPU#
CPU_STOP# - Assertion (transition from '1' to '0')
With the de-assertion of CPU_Stop# all stopped CPU outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 CPU clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped CPU outputs will be driven High within 10nS of CPU_Stop# de-assertion to
a voltage greater than 200mV.
CPU_Stop#
Tdrive_CPU_Stop, 10nS >200mV
CPU
CPU#
CPU Internal
CPU_STOP# - De-assertion (transition from '0' to '1')
16
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
PD# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power.
When PD# is asserted low all clocks will be driven low before turning off the VCO. In PD# de-assertion all clocks will start
without glitches.
PD#, Power Down
#
N
W
D
R
W
P
U
P
C
#
U
P
C
C
R
S
#
C
R
S
6
6
V
3
I
C
P
/
F
I
C
P
T
O
D
/
B
S
U
F
E
R
e
t
o
N
1
l
a
m
r
o
N
l
a
m
r
o
N
l
a
m
r
o
N
l
a
m
r
o
N
z
H
M
6
6
z
H
M
3
3
z
H
M
8
4
z
H
M
8
1
3
.
4
1
0
r
o
2
*
f
e
r
I
t
a
o
l
F
t
a
o
l
F
2
*
f
e
r
I
t
a
o
l
F
r
o
t
a
o
l
F
w
o
L
w
o
L
w
o
L
w
o
L
Notes:
1. Refer to tristate control of CPU and SRC clocks in section 7.7 for tristate timing and operation.
2. Refer to Control Registers in section 16 for CPU_Stop, SRC_Stop and PwrDwn SMBus tristate control addresses.
PD# should be sampled low by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be
held low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode but corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at
2 x Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.
PWRDWN#
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
PD# Assertion
17
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
The time from the de-assertion of PD# or until power supply ramps to get stable clocks will be less than 1.8ms. If the drive
mode control bit for PD# tristate is programmed to '1' the stopped differential pair must first be driven high to a minimum of
200mV in less than 300
s of PD# deassertion.
PWRDWN#
Tstable
<1.8mS
Tdrive_PwrDwn#
<300
S, >200mV
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC# 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
PD# De-assertion
The 3V66_4/VCH pin can be configured to be a 66.66MHz modulated output or a non-spread 48MHz output. The default is
3V66 clock. The switching is controlled by Byte 5 Bit 5. If it is set to '1' this pin will output the 48MHz VCH clock. The output
will go low on the falling edge of 3V66 for a minimum of 7.49ns. Then the output will transition to 48MHz on the next rising
edge of DOT_48 clock.
3V66
3V66_4/VCH
DOT_48
7.49nS min
3V66_4/VCH Pin Functionality
18
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or
tristated during PwrDwn# and CPU_Stop# mode and the SRC clock is configurable to be driven or tristated during
PCI_Stop# and PwrDwn# mode. Each differential clock (SRC, CPU[2:0]) output can be disabled by setting the
corresponding output's register OE bit to "0" (disable). Disabled outputs are to be tristated regardless of "CPU_Stop",
"SRC_Stop" and "PwrDwn" register bit settings.
l
a
n
g
i
S
#
D
P
n
i
P
n
i
P
#
p
o
t
S
_
U
P
C
p
o
t
S
_
U
P
C
t
i
B
e
t
a
t
s
i
r
T
n
w
d
r
w
P
t
i
B
e
t
a
t
s
i
r
T
e
l
b
a
p
p
o
t
S
-
n
o
N
s
t
u
p
t
u
O
e
l
b
a
p
p
o
t
S
s
t
u
p
t
u
O
}
0
:
2
[
U
P
C
1
1
X
X
g
n
i
n
n
u
R
g
n
i
n
n
u
R
}
0
:
2
[
U
P
C
1
0
0
X
g
n
i
n
n
u
R
6
x
f
e
r
I
@
n
e
v
i
r
D
}
0
:
2
[
U
P
C
1
0
1
X
g
n
i
n
n
u
R
e
t
a
t
s
i
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T
}
0
:
2
[
U
P
C
0
X
X
0
2
x
f
e
r
I
@
n
e
v
i
r
D
2
x
f
e
r
I
@
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D
}
0
:
2
[
U
P
C
0
X
X
1
e
t
a
t
s
i
r
T
e
t
a
t
s
i
r
T
Notes:
1. Each output has four corresponding control register bits, OE, PwrDwn, CPU_Stop and "Free Running"
2. Iref x 6 and Iref x 2 is the output current in the corresponding mode
3. See Control Registers section for bit address
l
a
n
g
i
S
#
D
P
n
i
P
n
i
P
#
p
o
t
S
_
I
C
P
p
o
t
S
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I
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d
r
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t
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b
a
p
p
o
t
S
t
u
p
t
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O
C
R
S
1
1
X
X
g
n
i
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u
R
g
n
i
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n
u
R
C
R
S
1
0
0
X
g
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u
R
6
x
f
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I
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S
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X
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t
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T
C
R
S
0
X
X
0
2
x
f
e
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I
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n
e
v
i
r
D
2
x
f
e
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X
X
1
e
t
a
t
s
i
r
T
e
t
a
t
s
i
r
T
Notes:
1. SRC output has four corresponding control register bits, OE, PwrDwn, SRC_Stop and "Free Running"
2. Iref x 6 and Iref x 2 is the output current in the corresponding mode
3. See Control Registers section for bit address
Differential Clock Tristate
19
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
The following diagrams illustrate CPU clock timing during CPU_Stop# and PwrDwn# modes with CPU_PwrDwn and
CPU_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
CPU_Stop = Driven, CPU_Pwrdwn = Driven
CPU_Stop#
1.8mS
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When both bits (CPU_Stop & CPU_Pwrdown tristate bits) are low, the clock chip will never tristate CPU output clocks
(assuming clock's OE bit is set to "1")
CPU Clock Tristate Timing
CPU_Stop = Tristate, CPU_Pwrdwn = Driven
CPU_Stop#
1.8mS
PD#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. Tristate outputs are pulled low by output termination resistors as shown here.
20
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
CPU_Stop = Driven, CPU_Pwrdwn = Tristate
CPU_Stop#
1.8mS
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When CPU_Pwrdwn is set to tristate and CPU_Stop is set to driven, the clock chip will tristate outputs only during the
assertion of PWRDWN#. Differential clock behavior during the assertion/de-assertion of CPU_Stop# will be unaffected.
2. In the case that CPU_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the CPU_Stop# high with the internal rising edges of clock#. This will result in CPU clocks resuming immediately
after the 1.8mS windows expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.
CPU_Stop = Tristate, CPU_Pwrdwn = Tristate
CPU_Stop#
1.8mS
PWRDWN#
CPU (Free Running)
CPU# (Free Running)
CPU (Stoppable)
CPU# (Stoppable)
Notes:
1. When CPU_Stop and CPU_Pwrdwn bits are set to tristate, the clock chip will tristate the outputs during the assertion of
CPU_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.
21
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
The following diagrams illustrate SRC clock timing during PCI_Stop# and PwrDwn# modes with SRC_Pwrdwn and
SRC_Stop tristate control bits set to driven or tristate in byte 2 of the control register.
SRC_Stop = Driven, SRC_Pwrdwn = Driven
PCI_Stop#
1.8mS
PWRDWN#
PCI (Free Running)
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
1 PCI
clock max
Notes:
1. When both bits (SRC_Stop & SRC_Pwrdown tristate bits) are set to driven, the clock chip will never tristate the SRC output
clock (assuming clock's OE bit is set to "1")
SRC Clock Tristate Timing
SRC_Stop = Tristate, Pwrdwn = Tristate
PCI_Stop#
1.8mS
PWRDWN#
PCI (Free Running)
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
1 PCI
clock max
Notes:
1. When SRC_Stop and SRC_Pwrdwn bits are set to tristate, the clock chip will tristate outputs during the assertion of
PCI_Stop# and PWRDWN#.
2. Tristate outputs are pulled low by output termination resistors as shown here.
22
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
PCI_STOP Asserted
SRC_Stop = Tristate, SRC_Pwrdwn = Tristate
PCI_Stop#
1.8mS
PWRDWN#
PCI (Free Running)
CPU (Free Running)
CPU# (Free Running)
SRC (Stoppable)
SRC# (Stoppable)
Notes:
1. When SRC_Pwrdwn and SRC_Stop are set to tristate, the clock chip will tristate outputs during the assertion of PCI_Stop#
and PWRDWN#.
2. In the case that PCI_Stop# is de-asserted during the 1.8mS PWRDWN# de-assertion resume delay, the clock chip can
sample the PCI_Stop# high with the internal rising edges of CPU clock#. This will result in SRC clocks resuming
immediately after the 1.8mS window expires. This applies to all control register bit changes as well.
3. Tristate outputs are pulled low by output termination resistors as shown here.
23
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
MIN
MAX
MIN
MAX
A
2.41
2.80
.095
.110
A1
0.20
0.40
.008
.016
b
0.20
0.34
.008
.0135
c
0.13
0.25
.005
.010
D
E
10.03
10.68
.395
.420
E1
7.40
7.60
.291
.299
e
h
0.38
0.64
.015
.025
L
0.50
1.02
.020
.040
N
a
0
8
0
8
VARIATIONS
MIN
MAX
MIN
MAX
56
18.31
18.55
.720
.730
10-0034
0.635 BASIC
0.025 BASIC
COMMON DIMENSIONS
In Millimeters
In Inches
COMMON DIMENSIONS
Reference Doc.: JEDEC Publication 95, MO-118
56-Lead, 300 mil Body, 25 mil, SSOP
N
SEE VARIATIONS
SEE VARIATIONS
D mm.
D (inch)
SYMBOL
SEE VARIATIONS
SEE VARIATIONS
INDEX
AREA
INDEX
AREA
1 2
N
D
h x 45
E1
E
SEATING
PLANE
SEATING
PLANE
A1
A
e
- C -
b
.10 (.004) C
.10 (.004) C
c
L
Ordering Information
ICS952601yFLFT
Example:
Designation for tape and reel packaging
Lead Free (optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS XXXX y F LF T
24
Integrated
Circuit
Systems, Inc.
ICS952601
0701G--10/13/04
INDEX
AREA
INDEX
AREA
1 2
1 2
N
D
E1
E
a
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
- C -
- C -
b
c
L
aaa
C
MIN
MAX
MIN
MAX
A
--
1.20
--
.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
D
E
E1
6.00
6.20
.236
.244
e
L
0.45
0.75
.018
.030
N
a
0
8
0
8
aaa
--
0.10
--
.004
VARIATIONS
MIN
MAX
MIN
MAX
56
13.90
14.10
.547
.555
10-0039
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil) (20 mil)
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
SEE VARIATIONS
SEE VARIATIONS
8.10 BASIC
0.319 BASIC
0.50 BASIC
0.020 BASIC
SEE VARIATIONS
SEE VARIATIONS
N
D mm.
D (inch)
Reference Doc.: JEDEC Publication 95, M O-153
Ordering Information
ICS952601yGLFT
Example:
Designation for tape and reel packaging
Lead Free (optional)
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
ICS XXXX y G LF T
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