M906-02 Datasheet Rev 0.6
Revision 013003
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
C o m m u n i c a t i o n s M o d u l e s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M906-02
VCSO B
ASED
C
LOCK
G
ENERATOR
Integrated
Circuit
Systems, Inc.
P r e l i m i n a r y I n f o r m a t i o n
G
ENERAL
D
ESCRIPTION
The M906-02 is a PLL (Phase Locked Loop) based
clock generator that uses an
internal VCSO (Voltage Controlled
SAW Oscillator) to produce a very
low jitter output clock. From the
M906-02-155.5200
, an output clock
frequency of
155.52
or
77.76
MHz is
provided from six LVPECL clock
output pairs. (Other frequencies are available; consult
factory.) The accuracy of the output frequency is
assured by the internal PLL that phase-locks the
internal VCSO to the reference input frequency
(
19.44
MHz for the
M906-02-155.5200
). The input reference
can either be an external crystal, utilizing the internal
crystal oscillator, or a stable external clock source
such as a packaged crystal oscillator.
F
EATURES
Output clock frequency range 75MHz
to 175MHz
(
For other output frequencies, consult factory)
Selectable divider chooses one of two frequencies
Six identical LVPECL output pairs (same frequency)
Jitter 0.7ps rms (over 12kHz-20MHz)
Ideal for
OC-48/STM-16
clock reference
Output-to-output skew < 100ps
External XTAL or LVCMOS reference input
Selectable external feed-through clock input
STOP clock control (Logic 1 stops output clocks)
Integrated SAW (surface acoustic wave) delay line
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
Figure 1: Pin Assignment
S
IMPLIFIED
B
LOCK
D
IAGRAM
Figure 2: Simplified Block Diagram
Example Output Frequency Configurations
(
M906-02-155.5200
)
Ref Clock
Frequency
(MHz)
VCSO
Frequency
(MHz)
P Divider
Value
Output
Frequency
(MHz)
19.44
155.52
1
155.52
2
77.76
Table 1: Example Output Frequency Configurations
M 9 0 6 - 0 2
( T o p V i e w )
1
2
3
4
5
6
7
8
9
XTA
L_
1
/
R
EF_
IN
GND
STO
P
EXT_
C
L
K
EN
_
EXT
_C
LK
FO
U
T
_
SEL
n
F
OUT
3
F
OUT3
VC
C
nFOUT2
FOUT2
nFOUT1
FOUT1
GND
nFOUT0
FOUT0
VCC
GND
XTAL_2
FOUT4
nFOUT4
FOUT5
nFOUT5
VCC
DNC
DNC
DNC
nOP
_
I
N
OP
_OUT
VC
nVC
nO
P_
O
U
T
OP
_I
N
GND
GND
GND
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
18
17
16
15
14
13
12
11
10
M906-02-155.52 (Other Frequencies Available)
O
1
Divider
Select
External
Crystal
or
Reference
Clock Input
(19.44MHz)
LVPECL
Output
Clock
Pairs
(155.52 or
77.76MHz)
Frequency
Multiplying
PLL
Divider
External
Clock
Input
External
Clock
Select
Output
Clock STOP
Control
External
Loop Filter
VSCO
XTAL
OSC
M906-02 VCSO Based Clock Generator
M906-02 Datasheet Rev 0.6
2 of 6
Revision 013003
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
C o m m u n i c a t i o n s M o d u l e s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
Integrated
Circuit
Systems, Inc.
M906-02
VCSO B
ASED
C
LOCK
G
ENERATOR
P r e l i m i n a r y I n f o r m a t i o n
D
ETAILED
B
LOCK
D
IAGRAM
Figure 3: Detailed Block Diagram
P
IN
D
ESCRIPTIONS
Number
Name
I/O
Configuration
Description
1,2,3,10,14,26 GND
Ground
Power supply ground.
4,9
OP_IN, nOP_IN
Input
Used for external loop filter. See
Figure 4
.
5,8
nOP_OUT, OP_OUT
Output
6, 7
nVC, VC
Input
11,19,33
VCC
Power
Power supply connection, connect to +
3.3
V
12,13
FOUT0, nFOUT0
Output
No internal terminator
Clock output pairs, differential LVPECL output
(
155.52
or
77.76
MHz for the
M906-02-155.5200
)
15,16
FOUT1, nFOUT1
17,18
FOUT2, nFOUT2
20,21
FOUT3, nFOUT3
29,30
FOUT4, nFOUT4
31,32
FOUT5, nFOUT5
22
FOUT_SEL
Input
Determines post-PLL divider value:
When
FOUT_SEL
=
1
, P =
1
When
FOUT_SEL
=
0
, P =
2
23
EN_EXT_CLK
Input
Internal pull-down
resistor
1
Note 1: For typical value of internal pull-down resistor, see
DC Characteristics
,
Pull-down
on
pg. 5
for typical value.
Logic 1 enables the
EXT_CLK
input.
Use Logic 0 for normal operation.
24
EXT_CLK
Input
External clock feed-through:
0
to
200
MHz
25
STOP
Input
Internal pull-down
resistor
1
Logic
1
stops clock outputs.
Use Logic
0
for normal operation.
27
XTAL_1 / REF_IN
Input
External crystal connection. Also accepts
LVCMOS/LVTTL compatible clock source.
28
XTAL_2
Input
External crystal connection. Leave unconnected
when driving pin
27
with external clock reference.
34,35,36
DNC
Do Not Connect. Internal test pins.
Table 2: Pin Descriptions
VCSO
M906-02
SAW Delay Line
Phase
Shifter
VCSO
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
R
IN
R
IN
OP_IN
nOP_IN
Phase
Detector
Loop Filter
Amplifier
External
Loop Filter
Components
XTAL_2
XTAL_1 / REF_IN
XTAL
OSC
M Divider
M = 8
O
1
EXT_CLK
EN_EXT_CLK
STOP
FOUT2
nFOUT2
FOUT4
nFOUT4
FOUT3
nFOUT3
FOUT5
nFOUT5
FOUT0
nFOUT0
FOUT1
nFOUT1
P Divider
P = 1 or 2
FOUT_SEL
Phase Locked Loop (PLL)
M906-02 Datasheet Rev 0.6
3 of 6
Revision 013003
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
C o m m u n i c a t i o n s M o d u l e s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M906-02
VCSO B
ASED
C
LOCK
G
ENERATOR
P r e l i m i n a r y I n f o r m a t i o n
Integrated
Circuit
Systems, Inc.
F
UNCTIONAL
D
ESCRIPTION
The M906-02 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks
synchronized to an input reference clock.
The M906-02 combines the flexibility of a VCSO
(Voltage Controlled SAW Oscillator) with the stability of
a crystal oscillator.
Input Reference
The
19.44
MHz input reference can either be an external,
discrete crystal device or a stable external clock source
such as a packaged crystal oscillator:
If an external crystal is used with the on-chip crystal
oscillator circuit (XTAL OSC), the external crystal
should be a parallel-resonant, fundamental mode
crystal. Apply it to the
XTAL_1 / REF_IN
and
XTAL_2
input
pins. External crystal load capacitors are also
required.
If an external LVCMOS/LVTTL clock source is used,
apply it to the
XTAL_1 / REF_IN
input pin.
In either case, the reference clock is supplied directly to
the phase detector of the PLL.
The EX_CLK pin is available for a clock feed-through
mode for testing. See
"External Clock Feed-through"
on
pg. 4
.
The PLL
The PLL (Phase Locked Loop) includes the phase
detector, the VCSO, and a feedback divider (labeled
"M Divider").
The feedback divider is a digital circuit that divides the
VCSO output frequency by a numerical value "M" in
order to match the input reference frequency.
By controlling the frequency and phase of the VCSO,
the phase detector precisely locks the frequency and
phase of the feedback divider output to that of the input
reference. This creates an output frequency that is a
multiple of the reference frequency (which is output
from the VCSO).
The relationship between the VCSO output frequency,
the M Divider, and the input reference frequency is
defined as follows:
For the
M906-02-155.5200 (see
"Ordering Information"
on
pg. 6
):
VCSO output frequency =
155.52
MHz
M =
8
Input reference frequency =
19.44
MHz
Therefore, for the
M906-02-155.5200
:
155.52
MHz =
8
19.44
MHz
The VCSO center output frequency of
155.52
MHz
enables the product of
to fall within the lock range of the VCSO.
Post-PLL Divider
The M906-02 also features a post-PLL divider (labeled
"P Divider") for selecting one of two output frequencies
(e.g., 155.52 or 77.76 MHz).
The
FOUT_SEL
pin determines the P Divider value:
When
FOUT_SEL
=
1
, P =
1
.
When
FOUT_SEL
=
0
, P =
2
.
External Loop Filter
To provide stable PLL operation, and thereby a low jitter
output clock, the M906-02 requires the use of an
external loop filter. This is provided via the provided
filter pins (see
Figure 4
).
Due to the differential signal path design, the
implementation requires two identical complementary
RC filters as shown here.
Figure 4: External Loop Filter
Fvcso
M
Fxtal
=
External Loop Filter Component Values
PLL
Bandwidth
Damping
Factor
R loop
C loop R post
C post
395
Hz
2.0
1.5
k
4.70
F
20
k
3300
pF
1.2
kHz
2.9
4.7
k
1.00
F
20
k
1000
pF
10
kHz
1
Note 1: Recommended for most applications
2.4
39.0
k
0.01
F
20
k
240
pF
Table 3: External Loop Filter Component Values
M
input crystal frequency
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN
nOP_IN
6
7
5
4
9
8
M906-02 Datasheet Rev 0.6
4 of 6
Revision 013003
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
C o m m u n i c a t i o n s M o d u l e s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
Integrated
Circuit
Systems, Inc.
M906-02
VCSO B
ASED
C
LOCK
G
ENERATOR
P r e l i m i n a r y I n f o r m a t i o n
External Clock Feed-through
The
EXT_CLK
pin provides an input for an external
single-ended clock that directly drives the LVPECL
clock outputs. In application, this may be used for
system debugging and performance evaluation.
1. Set pin
EN_EXT_CLK
to Logic 1.
2. Apply an external LVCMOS/LVTTL clock source
to the
EXT_CLK
input pin.
Due to the fact that EXT_CLK bypasses the PLL,
any frequency between DC and 200MHz can be
used.
STOP Clock
The
STOP
pin puts the output clock into a static condition.
Logic 1 Output clocks are static
Logic 0 Output clocks enabled for normal operation
A
BSOLUTE
M
AXIMUM
R
ATINGS
1
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings ard stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in
Recommended Conditions of Operation
,
DC Characteristics
, or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Symbol Parameter
Rating
Unit
V
I
Inputs
-
0.5
to V
CC
+
0.5
V
V
O
Outputs
-
0.5
to V
CC
+
0.5
V
CC
Power Supply Voltage
4.6
T
S
Storage Temperature
-
45
to +
100
o
C
Table 4: Absolute Maximum Ratings
R
ECOMMENDED
C
ONDITIONS
OF
O
PERATION
Symbol Parameter
Min
Typ
Max
Unit
V
CC
Positive Supply Voltage
3.135
3.3
3.465
V
T
A
Ambient Operating Temperature
0
+
70
o
C
Table 5: Recommended Conditions of Operation
M906-02 Datasheet Rev 0.6
5 of 6
Revision 013003
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
C o m m u n i c a t i o n s M o d u l e s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M906-02
VCSO B
ASED
C
LOCK
G
ENERATOR
P r e l i m i n a r y I n f o r m a t i o n
Integrated
Circuit
Systems, Inc.
E
LECTRICAL
S
PECIFICATIONS
DC Characteristics
Unless stated otherwise, V
CC
= 3.3 Volts + 5%, T
A
= 0
o
C to 70
o
C, Output Frequency=155.52MHz
1
, Outputs terminated with 50
to V
CC
- 2V
Symbol Parameter
Min
Typ
Max
Unit
Power Supply
V
CC
Positive Supply Voltage
3.135
3.3
3.465
V
I
CC
Power Supply Current
300
mA
Logic Inputs
V
IH
Input High Voltage
FOUT_SEL, EN_EXT_CLK,
EXT_CLK, STOP
2
V
cc
+
0.3
V
V
IL
Input Low Voltage
-
0.3
0.8
V
I
IH
Input High Current
150
A
I
IL
Input Low Current
-
5.0
A
Reference
Clock
Input
V
IH
Input High Voltage
XTAL_1 / REF_IN
(XTAL_2 disconnected)
(V
cc
/
2
) +
0.5
V
cc
+
0.3
V
V
IL
Input Low Voltage
-
0.3
(V
cc
/
2
) +
0.5
V
I
IH
Input High Current
150
A
I
IL
Input Low Current
-
5.0
A
All Inputs
C
IN
Input Capacitance, All Inputs
FOUT_SEL,
EN_EXT_CLK, EXT_CLK,
STOP, XTAL_1 / REF_IN
4
pF
Pull-down
R
pulldown
Internal Pull-down Resistor
EN_EXT_CLK, STOP
51
k
Differential
Output
V
OH
Output High Voltage
FOUT, nFOUT (0-5)
V
cc
-
1.4
V
cc
-
1.0
V
V
OL
Output Low Voltage
V
cc
-
2.0
V
cc
-
1.7
V
V
P
-
P
Peak to Peak Output Voltage
0.6
0.
85
V
Table 6: DC Characteristics
Note 1: For other VCSO center frequencies, contact ICS
AC Characteristics
Unless implied otherwise, V
CC
= 3.3 Volts + 5%, T
A
= 0
o
C to 70
o
C, Output Frequency=155.52MHz
1
, Outputs terminated with 50
to V
CC
- 2V
Symbol Parameter
Min
Typ
Max
Unit
Test Conditions
F
OUT
Output Frequency Range
75
175
MHz
FOUT_SEL
=1
1
F
IN
Nominal Input Frequency,
XTAL_1 / REF_IN
19.44
MHz
APR
VCSO Pull-Range
+
100
+
150
ppm
n
Single Side Band
Phase Noise
@
155.52
MHz
1
kHz Offset
-
100
dBc/Hz
10
kHz Offset
-
110
dBc/Hz
100
kHz Offset
-
134
dBc/Hz
J(t)
Jitter (rms)
0.7
1.0
ps
12
kHz to
20
MHz
t
DC
Output Duty Cycle, High Time
45
50
55
%
t
R
Output Rise Time
FOUT, nFOUT (0-5)
350
450
550
ps
20
% to
80
%
t
F
Output Fall Time
FOUT, nFOUT (0-5)
350
450
550
ps
20
% to
80
%
t
S
Output Skew
Between Any Pair
100
ps
EXT_CLK
Frequency
EXT_CLK
0
200
MHz
Table 7: AC Characteristics
Note 1: For other VCSO center frequencies, contact ICS
M906-02 Datasheet Rev 0.6
6 of 6
Revision 013003
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
C o m m u n i c a t i o n s M o d u l e s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
Integrated
Circuit
Systems, Inc.
M906-02
VCSO B
ASED
C
LOCK
G
ENERATOR
P r e l i m i n a r y I n f o r m a t i o n
P
ACKAGE
- M
ECHANICAL
D
IMENSIONS
O
RDERING
I
NFORMATION
Other frequencies available upon request.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
KEY to Dimensions
e.g., .016 [0.4]
INCHES [MM]
For Output Frequencies (MHz)
Order Part Number
155.52
M906-02-155.5200
77.76
Table 8: Ordering Information
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