MK1581-01
MDS 1581-01 C
1
Revision 050803
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 295-9800
www.icst.com
Low Phase Noise T1 / E1 Clock Generator
Description
The MK1581-01 provides synchronization and timing
control for T1 and E1 based network access or
multitrunk telecommunication systems. The device
accepts an 8 kHz frame clock input and uses an
on-chip VCXO to produce a synchronized low phase
noise clock output.
This monolithic IC, combined with an external
inexpensive quartz crystal, can be used to replace a
more costly hybrid VCXO retiming module. Through
selection of external loop filter components values, the
device can be tailored to meet the system's clock jitter
attenuation requirements. Low-pass jitter attenuation
characteristics in the Hz range are possible.
Features
Generates a T1 (1.544 MHz) or E1 (2.048 MHz)
output clock from an 8kHz frame clock input
Configurable jitter attenuation characteristics,
excellent for use as a Stratum source de-jitter circuit
VCXO-based clock generation ensures very low jitter
and phase noise generation
Output clock is phase and frequency locked to the
input reference clock
+115ppm minimum crystal frequency pullability
range, using recommended crystal
Industrial temperature range
Low power CMOS technology
16 pin TSSOP package
Single 3.3V power supply
Block Diagram
Charge
Pump
VCXO
Pullable Crystal
Output
Divider
Feedback
Divider
8kHz_IN
CLK
X2
X1
ISET
VDD
3
VDD
VIN
CHGP
5
GND
SEL
Phase
Detector
C
P
C
S
R
S
R
SET
Low Phase Noise T1 / E1 Clock Generator
MDS 1581-01 C
2
Revision 050803
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 295-9800
www.icst.com
MK1581-01
Pin Assignment
16 pin 4.40 mil body, 0.65 mm pitch TSSOP
Output Clock Selection Table
Pin Descriptions
12
1
11
2
10
VDD
X1
3
9
VDD
4
VDD
X2
5
VIN
6
8kHz_IN
7
GND
8
GND
SEL
CLK
GND
GND
GND
CHGP
ISET
16
15
14
13
Input
Clock
SEL
Output
Clock
(MHz)
Crystal
Used (MHz)
8 kHz
0
1.544
24.704
8 kHz
1
2.048
24.576
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
VDD
Power
Power Supply. Connect to +3.3V.
2
VDD
Power
Power Supply. Connect to +3.3V.
3
VDD
Power
Power Supply. Connect to +3.3V.
4
VIN
Input
VCXO Control Voltage Input. Connect this pin to CHGP pin and the external
loop filter as shown in this data sheet.
5
GND
Power
Connect to ground
6
GND
Power
Connect to ground
7
GND
Power
Connect to ground
8
CHGP
Output
Charge Pump Output. Connect this pin to the external loop filter and to pin
VIN.
9
ISET
-
Charge pump current setting node, connection for setting resistor.
10
GND
Power
Connect to ground.
11
GND
Power
Connect to ground.
12
CLK
Output
Clock Output
13
SEL
Input
Output Frequency Selection. Determines output frequency as per table above.
Internal pull-up.
14
8kHz_IN
Input
8 kHz reference clock input.
15
X2
-
Crystal Output. Connect this pin to the specified crystal.
16
X1
-
Crystal Input. Connect this pin to the specified crystal.
Low Phase Noise T1 / E1 Clock Generator
MDS 1581-01 C
3
Revision 050803
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 295-9800
www.icst.com
MK1581-01
Functional Description
The MK1581-01 is a clock generator IC that generates
a T1 or E1 reference clock directly from an internal
VCXO circuit that works in conjunction with an external
quartz crystal. The VCXO output frequency and phase
is controlled by an internal PLL (Phase Locked Loop)
circuit, enabling the device to perform clock
regeneration from an 8 kHz input reference clock.
Most typical PLL clock devices use an internal VCO
(Voltage Controlled Oscillator) for output clock
generation. By using a VCXO with an external crystal,
the MK1581-01 is able to generate a low jitter, low
phase-noise output clock. The low bandwidth capability
of the PLL circuit serves to provide input clock jitter
attenuation and enables stable operation with the low
frequency input reference clock.
The internal VCXO circuit requires an external pullable
crystal for operation. External loop filter components
enable a PLL configuration with low loop bandwidth.
Application Information
Output Frequency Configuration
The MK1581-01 is configured to generate either a
1.544 MHz T1 clock or a 2.048 MHz E1 clock from an
8kHz input clock. Please refer to the Output Clock
Selection Table on Page 2. Input bit SEL is set
according to this table, as is the external crystal
frequency. Please refer to the Quartz Crystal section on
this page regarding external crystal requirements.
Quartz Crystal
It is important that the correct type of quartz crystal is
used with the MK1581-01. Failure to do so may result in
reduced frequency pullability range, inability of the loop
to lock, or excessive output phase jitter.
The MK1581-01 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input.
The VCXO consists of the external crystal and the
integrated VCXO oscillator circuit. To achieve the best
performance and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the PCB
Layout Recommendations section must be followed.
The frequency of oscillation of a quartz crystal is
determined by its cut and by the external load
capacitance. The MK1581-01 incorporates variable
load capacitors on-chip which "pull", or change, the
frequency of the crystal. The crystals specified for use
with the MK1581-01 are designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14pF. To achieve this, the layout should
use short traces between the MK1581-01 and the
crystal.
A complete description of the recommended crystal
parameters is in application note MAN05.
A list of approved crystals is located on the ICST web
site (www.icst.com).
PLL Loop Filter Components
A phased-locked loop (PLL) is a control system that
keeps the VCO frequency and phase locked with the
input reference clock. Like all control systems, analog
PLL circuits use a loop filter to establish operating
stability. The MK1581-01 uses external loop filter
components for the following reasons:
1) Larger loop filter capacitor values can be used,
allowing a lower loop bandwidth. This enables the use
of lower input clock reference frequencies and also
input clock jitter attenuation capabilities. Larger loop
filter capacitors also allow higher loop damping factors
when less passband peaking is desired.
2) The loop filter values can be user selected to
optimize loop response characteristics for a given
application.
Referencing the External Component Schematic on
this page, the external loop filter is made up of
components R
S
, C
S
and C
P
. R
SET
establishes PLL
charge pump current and therefore influences loop
filter characteristics.
Design aid tools for configuring the loop filter can be
found at www.icst.com, including on-line and PC-based
calculators.
Low Phase Noise T1 / E1 Clock Generator
MDS 1581-01 C
4
Revision 050803
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 295-9800
www.icst.com
MK1581-01
External Component Schematic
Recommended Loop Filter Values Vs. Output Frequency Selection
SEL Output Freq
Crystal
Multiplier
(N)
R
SET
R
S
C
S
C
P
Loop
Bandwidth
(-3dB point)
Damping
Factor
0
1.544 MHz
3088
120 k
W
1.0 M
W
0.1
m
F
4.7 nF
18 Hz
1.4
1
2.048 MHz
3072
120 k
W
1.0 M
W
0.1
m
F
4.7 nF
19 Hz
1.4
C
S
R
SET
R
S
C
P
Refer to Crystal Tuning section
12
1
11
2
10
VDD
X1
3
9
VDD
4
VDD
X2
5
VIN
6
8kHz_IN
7
GND
8
GND
SEL
CLK
GND
GND
GND
CHGP
ISET
16
15
14
13
C
L
C
L
Pullable
Crystal
Low Phase Noise T1 / E1 Clock Generator
MDS 1581-01 C
5
Revision 050803
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 295-9800
www.icst.com
MK1581-01
A "normalized" PLL loop bandwidth may be calculated
as follows:
The "normalized" bandwidth (NBW) equation above
does not take into account the effects of damping factor
or the second pole. NBW is approximately equal to the
actual -3dB bandwidth of the loop when the damping
factor is about 5 and C
2
is very small. In most
applications, NBW is about 75% of the actual -3dB
bandwidth. However, NBW does provide a useful
approximation of filter performance.
The loop damping factor is calculated as follows:
Where:
R
S
= Value of resistor in loop filter (Ohms)
I
CP
= Charge pump current (amps)
(refer to Charge Pump Current Table, below)
N = Crystal multiplier shown in the above table
C
S
= Value of capacitor C
S
in loop filter
(Farads)
As a general rule, the following relationship should be
maintained between components C
S
and C
P
in the loop
filter:
Charge Pump Current Table
Special considerations must be made in choosing loop
components C
S
and C
P
.
These recommendations can be found in the design
aid tools section of www.icst.com.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50
W
trace (a
commonly used trace impedance), place a 33
W
resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20
W
. (The optional series termination resistor
is not shown in the External Component Schematic.)
Decoupling Capacitors
As with any high performance mixed-signal IC, the
MK1581-01 must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01F must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the MK1581-01 should use one common connection to
the PCB power plane as shown in the diagram on the
next page. The ferrite bead and bulk capacitor help
reduce lower frequency noise in the supply that can
lead to output clock phase modulation.
Recommended Power Supply Connection
for Optimal Device Performance
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground, shown as C
L
in the External Component
Schematic. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
R
SET
Charge Pump Current
(I
CP
)
1.4 M
W
10
m
A
680 k
W
20
m
A
540 k
W
25
m
A
120 k
W
100
m
A
NBW
R
S
I
CP
575
N
---------------------------------------
=
Damping Factor
R
S
625
I
CP
C
S
N
-----------------------------------------
=
C
P
C
S
20
------
=
C onnection to 3.3V
P ow er P lane
Ferrite
Bead
B ulk D ecoupling C apac itor
(such as 1
F Tantalum )
V D D P in
V D D P in
V D D P in
0.01
F D ecoupling C apacitors
Low Phase Noise T1 / E1 Clock Generator
MDS 1581-01 C
6
Revision 050803
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 295-9800
www.icst.com
MK1581-01
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
been the crystal and device.
In most cases the load capacitors will not be required.
They should not be stuffed on the prototype evaluation
board as the indiscriminate use of these trim capacitors
will typically cause more crystal centering error than
their absence. If the need for the load capacitors is later
determined, the values will fall within the 1-4 pf range.
The need for, and value of, these trim capacitors can
only be determined at prototype evaluation. Refer to
MAN05 for the centering capacitor selection procedure.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed. Please also refer to the Recommended PCB
Layout drawing on Page 7.
1) Each 0.01F decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible. No via's should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible,
as should the PCB trace to the ground via. Distance of
the ferrite bead and bulk decoupling from the device is
less critical.
2) The loop filter components must also be placed
close to the CHGP and VIN pins. C
P
should be closest
to the device. Coupling of noise from other system
signal traces should be minimized by keeping traces
short and away from active signal traces. Use of vias
should be avoided.
3) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
4) To minimize EMI the 33
W
series termination resistor,
if needed, should be placed close to the clock output.
5) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (the ferrite bead and bulk decoupling
capacitor can be mounted on the back). Other signal
traces should be routed away from the MK1581-01.
This includes signal traces just underneath the device,
or on layers adjacent to the ground plane layer used by
the device.
The ICS Applications Note MAN05 may also be
referenced for additional suggestions on layout of the
crystal section.
Low Phase Noise T1 / E1 Clock Generator
MDS 1581-01 C
7
Revision 050803
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 295-9800
www.icst.com
MK1581-01
Recommended PCB Layout
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK1581-01. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5V to VDD+0.5V
Ambient Operating Temperature
-40 to +85
C
Storage Temperature
-65 to +150
C
Junction Temperature
175
C
Soldering Temperature
260
C
G
For m inim um output clock jitter,
rem ove ground and pow er plane
w ithin this entire area. A lso route
all other traces aw ay from this area.
= G round
C onnection
G
G
G
G
G
Legend:
For m inim um output clock jitter,
device V D D connections should
be m ade to com m on bulk
decoupling device (see text).
1
2
3
4
5
6
7
8
12
11
10
9
16
15
14
13
G
G
G
G
G
Low Phase Noise T1 / E1 Clock Generator
MDS 1581-01 C
8
Revision 050803
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 295-9800
www.icst.com
MK1581-01
Recommended Operation Conditions
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85
C
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85
C
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature
-40
+85
C
Power Supply Voltage (measured in respect to GND)
+3.15
+3.3
+3.45
V
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.15
3.3
3.45
V
Supply Current
IDD
Clock outputs
unloaded, VDD = 3.3V
10
15
mA
Input High Voltage, SEL
V
IH
2
V
Input Low Voltage, SEL
V
IL
0.8
V
Input High Voltage, 8kHz_IN
V
IH
VDD/2+1
V
Input Low Voltage, 8kHz_IN
V
IL
VDD/2-1
V
Input High Current
I
IH
V
IH
= VDD
-10
+10
m
A
Input Low Current
I
IL
V
IL
= 0
-10
+10
m
A
Input Capacitance, except X1
C
IN
7
pF
Output High Voltage (CMOS
Level)
V
OH
I
OH
= -4 mA
VDD-0.4
V
Output High Voltage
V
OH
I
OH
= -8 mA
2.4
V
Output Low Voltage
V
OL
I
OL
= 8 mA
0.4
V
Short Circuit Current
I
OS
50
mA
VIN, VCXO Control Voltage
V
XC
0
VDD
V
Nominal Output Impedance
Z
OUT
20
W
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
VCXO Crystal Pull Range
f
XP
Using Recommended
Crystal
-115
+115
ppm
VCXO Crystal Nominal
Frequency
f
X
24.704
24.576
MHz
Input Jitter Tolerance
t
ji
In reference to input
clock period
0.4
UI
Input pulse width (1)
t
pi
10
ns
Output Frequency Error
F
OUT
ICLK = 0 ppm error
0
0
0
ppm
Output Duty Cycle (% high
time)
t
OD
Measured at VDD/2,
C
L
=15pF
40
60
%
Low Phase Noise T1 / E1 Clock Generator
MDS 1581-01 C
9
Revision 050803
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 295-9800
www.icst.com
MK1581-01
Note 1: Minimum high or low time of input clock.
Note 2: The input to output clock skew is not controlled nor predictable and will change between power up
cycles. Because it is dependent on the phase relationship between the output and feedback divider states
following power up, the input to output clock skew will remain stable during a given power up cycle. If
controlled input to output skew is desired for this output clock frequency please refer to the MK2049 or
MK2069 products.
Thermal Characteristics
Output Rise Time
t
OR
0.8 to 2.0V, C
L
=15pF
1.5
ns
Output Fall Time
t
OF
2.0 to 0.8V, C
L
=15pF
1.5
ns
Skew, Input to Output Clock
t
IO
Note 2
Cycle Jitter (short term jitter)
t
ja
Peak to Peak
150
ps p-p
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Thermal Resistance Junction to
Ambient
q
JA
Still air
78
C/W
q
JA
1 m/s air flow
70
C/W
q
JA
3 m/s air flow
68
C/W
Thermal Resistance Junction to Case
q
JC
37
C/W
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Low Phase Noise T1 / E1 Clock Generator
MDS 1581-01 C
10
Revision 050803
Integrated Circuit Systems, Inc.
525 Race Street, San Jose, CA 95126
tel (408) 295-9800
www.icst.com
MK1581-01
Package Outline and Package Dimensions
(16 pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Ordering Information
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
Part / Order Number
Marking
Shipping
packaging
Package
Temperature
MK1581-01GI
MK1581-01GI
Tubes
16 pin TSSOP
-40 to +85
C
MK1581-01GITR
MK1581-01GI
Tape and Reel
16 pin TSSOP
-40 to +85
C
IN D E X
A R E A
1 2
16
D
E 1
E
S E A T IN G
P LA N E
A
1
A
A
2
e
- C -
b
aa a
C
c
L
Millimeters
Inches
Symbol
Min
Max
Min
Max
A
--
1.20
--
0.047
A1
0.05
0.15
0.002
0.006
A2
0.80
1.05
0.032
0.041
b
0.19
0.30
0.007
0.012
C
0.09
0.20
0.0035
0.008
D
4.90
5.1
0.193
0.201
E
6.40 BASIC
0.252 BASIC
E1
4.30
4.50
0.169
0.177
e
0.65 Basic
0.0256 Basic
L
0.45
0.75
0.018
0.030
a
0
8
0
8
aaa
--
0.10
--
0.004
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