Philips Semiconductors

Product data sheet

PCA9513; PCA9514

Hot swappable I

C and SMBus bus buffer

2004 Oct 05

DESCRIPTION

The PCA9513 and PCA9514 are hot swappable I

C and SMBus

buffers that allows I/O card insertion into a live backplane without
corrupting the data and clock buses. Control circuitry prevents the
backplane from being connected to the card until a stop command
or bus idle occurs on the backplane without bus contention on the
card. When the connection is made, the PCA9511, PCA9513, and
PCA9514 provides bi-directional buffering, keeping the backplane
and card capacitances isolated.

Rise time accelerator circuitry allows the use of weaker DC pull-up
currents while still meeting rise time requirements. The PCA9513
and PCA9514 incorporate a digital ENABLE input pin, which
enables the device when asserted HIGH and forces the device into
a low current mode when asserted LOW, and an open-drain READY
output pin, which indicates that the backplane and card sides are
connected together (HIGH) or not (LOW).

The PCA9513 supplies a 92

A current source to SCLIN and SDAIN

in lieu of using pull-up resistors for PICMG backplane applications.
Including the current source in the device provides for a consistent
RC time constant as cards are removed and inserted into the
backplane. The current source is high-impedance whenever the pin
voltage is greater than the part V

PCA9513 and PCA9514 rise time accelerator threshold is 0.8 V to
provide improved noise margin over the PCA9510 and PCA9511.

The dynamic offset design of the PCA9510/11/12/13/14 I/O drivers
allow them to be connected to another PCA9510/11/12/13/14 device
in series or in parallel and to the A side of the PCA9517. The
PCA9510/11/12/13/14 can not connect to the static offset I/Os used
on the PCA9515/15A/16/16A/17 B side and PCA9518.

APPLICATION

cPCI, VME, AdvancedTCA cards and other multi-point backplane
cards that are required to be inserted or removed from an
operating system.

FEATURES

Bi-directional buffer for SDA and SCL lines increases fanout and
prevents SDA and SCL corruption during live board insertion and
removal from multi-point backplane systems

Compatible with I

C standard mode, I

C fast mode, and SMBus

standards

t rise time accelerators on all SDA and SCL lines

Rise time accelerator threshold moved from 0.6 V to 0.8 V for
improved noise margin

Active HIGH ENABLE input

Active HIGH READY open-drain output

High-impedance SDA and SCL pins for V

= 0 V

A current source on SCLIN and SDAIN for PICMG backplane

applications (PCA9513 only)

Supports clock stretching and multiple master
arbitration/synchronization

Operating power supply voltage range: 2.7 V to 5.5 V

5.5 V tolerant I/Os

0 kHz to 400 kHz clock frequency

ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115, and 1000 V CDM per
JESD22-C101

Latch-up testing is done to JEDEC Standard JESD78 which
exceeds 100 mA

Packages offered: SO8, TSSOP8 (MSOP8)

ORDERING INFORMATION

PACKAGES

TEMPERATURE RANGE

ORDER CODE

TOPSIDE MARK

DRAWING NUMBER

8-pin plastic SO

C to +85

PCA9513D

PCA9513

SOT96-1

8-pin plastic SO

C to +85

PCA9514D

PCA9514

SOT96-1

8-pin plastic TSSOP (MSOP)

C to +85

PCA9513DP

9513

SOT505-1

8-pin plastic TSSOP (MSOP)

C to +85

PCA9514DP

9514

SOT505-1

Standard packing quantities and other packaging data are available at www.standardproducts.philips.com/packaging.

Philips Semiconductors

Product data sheet

PCA9513; PCA9514

Hot swappable I

C and SMBus bus buffer

2004 Oct 05

PIN CONFIGURATION

ENABLE

GND

SCLIN

SDAOUT

SDAIN

READY

SCLOUT

SW01045

TOP VIEW

Figure 1. Pin configuration.

PIN DESCRIPTION

PIN

SYMBOL

DESCRIPTION

ENABLE

Chip enable pin. Grounding this pin puts the
part in a low current (< 1

A) mode. It also

disables the rise time accelerators, isolates
SDAIN from SDAOUT and isolates SCLIN
from SCLOUT.

SCLOUT

Serial clock output to and from the SCL bus
on the card.

SCLIN

Serial clock input to and from the SCL bus
on the backplane.

GND

Ground. Connect this pin to a ground plane
for best results.

READY

This is an open-drain output which pulls
LOW when SDAIN and SCLIN are
disconnected from SDAOUT and SCLOUT,
and turns off when the two sides are
connected.

SDAIN

Serial data input to and from the SDA bus on
the backplane.

SDAOUT

Serial data output to and from the SDA bus
on the card.

Power supply.

FEATURE SELECTION CHART

FEATURES

PCA9510

PCA9511

PCA9512

PCA9513

PCA9514

Idle detect

Yes

high-impedance SDA, SCL pins for V

= 0 V

Yes

Rise time accelerator circuitry on all SDA and SCL lines

Yes

Rise time accelerator circuitry hardware disable pin for lightly loaded systems

Yes

Rise time accelerator threshold 0.8 V vs 0.6 V improves noise margin

Yes

Ready open drain output

Yes

Two V

pins to support 5 V to 3.3 V level translation with improved noise

margins

Yes

1 V precharge on all SDA and SCL lines

IN only

Yes

A current source on SCLIN and SDAIN for PICMG applications

Yes

Philips Semiconductors

Product data sheet

PCA9513; PCA9514

Hot swappable I

C and SMBus bus buffer

2004 Oct 05

OPERATION

Start-up

An under voltage/initialization circuit holds the parts in a
disconnected state which presents high-impedance to all SDA and
SCL pins during power-up. A LOW on the enable pin also forces the
parts into the low current disconnected state when the I

essentially zero. As the power supply is brought up and the enable
is HIGH or the part is powered and the enable is taken from LOW to
HIGH it enters an initialization state where the internal references
are stabilized. The 92

A input pull-ups on PCA9513 are also

enabled in the initialization state. At the end of the initialization state
the "Stop Bit And Bus Idle" detect circuit is enabled. With the
ENABLE pin HIGH long enough to complete the initialization state
and remaining HIGH when all the SDA and SCl pins have been
HIGH for the bus idle time or when all pins are HIGH and a stop
condition is seen on the SDAIN and SCLIN pins, SDAIN is
connected to SDAOUT and SCLIN is connected to SCLOUT.

A 92

A pull-up current source on SDAIN and SCLIN of PCA9513 is

activated during the initialization state and remain active until the
power is removed or the enable is taken LOW. When the 92

pull-up is active it will become high-impedance any time the pin
voltage is greater than V

, otherwise it provides current to pull the

pin up to V

Connect Circuitry

Once the connection circuitry is activated, the behavior of SDAIN
and SDAOUT as well as SCLIN and SCLOUT become identical with
each acting as a bidirectional buffer that isolates the input
capacitance from the output bus capacitance while communicating
the logic levels. A LOW forced on either SDAIN or SDAOUT will
cause the other pin to be driven to a LOW by the part. The same is
also true for the SCL pins. Noise between 0.7V

and V

generally ignored because a falling edge is only recognized when it
falls below 0.7V

with a slew rate of at least 1.25 V/

s. When a

falling edge is seen on one pin the other pin in the pair turns on a
pull down driver that is referenced to a small voltage above the
falling pin. The driver will pull the pin down at a slew rate determined
by the driver and the load initially, because it does not start until the
first falling pin is below 0.7V

. The first falling pin may have a fast

or slow slew rate, if it is faster than the pull down slew rate then the
initial pull down rate will continue. If the first falling pin has a slow
slew rate then the second pin will be pulled down at its initial slew
rate only until it is just above the first pin voltage the they will both
continue down at the slew rate of the first.

Once both sides are LOW they will remain LOW until all the external
drivers have stopped driving LOWs. If both sides are being driven
LOW to the same value for instance, 10 mV by external drivers,
which is the case for clock stretching and is typically the case for
acknowledge, and one side external driver stops driving that pin will
rise and rise above the nominal offset voltage until the internal driver
catches up and pulls it back down to the offset voltage. This bounce
is worst for low capacitances and low resistances, and may become
excessive. When the last external driver stops driving a LOW, that
pin will bounce up and settle out just above the other pin as both rise
together with a slew rate determined by the internal slew rate control
and the RC time constant. As long as the slew rate is at least
1.25 V/

s, when the pin voltage exceeds 0.8 V for PCA9513 and

PCA9514, rise time accelerators circuits are turned on and the pull
down driver is turned off.

Maximum number of devices in series

Each buffer adds about 0.065 V dynamic level offset at 25

C with

the offset larger at higher temperatures. Maximum offset (V

) is

0.150 V. The LOW level at the signal origination end (master) is
dependent upon the load and the only specification point is the
I

C-bus specification of 3 mA will produce V

< 0.4 V, although if

lightly loaded the V

may be

0.1 V. Assuming V

= 0.1 V and

= 0.1 V, the level after four buffers would be 0.5 V, which is only

about 0.1 V below the threshold of the rising edge accelerator (about
0.6 V). With great care a system with four buffers may work, but as
the V

moves up from 0.1 V, noise or bounces on the line will result

in firing the rising edge accelerator thus introducing false clock
edges. Generally it is recommended to limit the number of buffers in
series to two.

The PCA9510 (rise time accelerator is permanently disabled) and
the PCA9512 (rise time accelerator can be turned off) are a little
different with the rise time accelerator turned off because the rise
time accelerator will not pull the node up, but the same logic that
turns on the accelerator turns the pull-down off. If the V

is above

0.6 V and a rising edge is detected, the pull-down will turn off and

will not turn back on until a falling edge is detected; so if the noise is
small enough it may be possible to use more than two PCA9510 or
PCA9512 parts in series but is not recommended.

MASTER

buffer A

SLAVE B

buffer B

SLAVE C

buffer C

SW02353

common

node

Figure 6.

Consider a system with three buffers connected to a common node
and communication between the Master and Slave B that are
connected at either end of Buffer A and Buffer B in series as shown
in Figure 6. Consider if the V

at the input of Buffer A is 0.3 V and

the V

of Slave B (when acknowledging) is 0.4 V with the direction

changing from Master to Slave B and then from Slave B to Master.
Before the direction change you would observe V

at the input of

Buffer A of 0.3 V and its output, the common node, is

0.4 V. The

output of Buffer B and Buffer C would be

0.5 V, but Slave B is

driving 0.4 V, so the voltage at Slave B is 0.4 V. The output of
Buffer C is

0.5 V. When the Master pull-down turns off, the input of

Buffer A rises and so does its output, the common node, because it
is the only part driving the node. The common node will rise to 0.5 V
before Buffer B's output turns on, if the pull-up is strong the node will
bounce. If the bounce goes above the threshold for the rising edge
accelerator

0.6 V the accelerators on both Buffer A and Buffer C

will fire contending with the output of Buffer B. The node on the input
of Buffer A will go HIGH as will the input node of Buffer C. After the
common node voltage is stable for a while the rising edge
accelerators will turn off and the common node will return to

0.5 V

because the Buffer B is still on. The voltage at both the Master and
Slave C nodes would then fall to

0.6 V until Slave B turned off. This

would not cause a failure on the data line as long as the return to
0.5 V on the common node (

0.6 V at the Master and Slave C)

occurred before the data setup time. If this were the SCL line, the
parts on Buffer A and Buffer C would see a false clock rather than a
stretched clock, which would cause a system error.

Philips Semiconductors

Product data sheet

PCA9513; PCA9514

Hot swappable I

C and SMBus bus buffer

2004 Oct 05

Propagation Delays

The delay for a rising edge is determined by the combined pull-up
current from the bus resistors and the rise time accelerator current
source and the effective capacitance on the lines. If the pull-up
currents are the same, any difference in rise time is directly
proportional to the difference in capacitance between the two sides.
The t

PLH

may be negative if the output capacitance is less than the

input capacitance and would be positive if the output capacitance is
larger than the input capacitance, when the currents are the same.

The t

PHL

can never be negative because the output does not start to

fall until the input is below 0.7V

, and the output turn on has a non

zero delay, and the output has a limited maximum slew rate, and
even if the input slew rate is slow enough that the output catches up
it will still lag the falling voltage of the input by the offset voltage. The
maximum t

PHL

occurs when the input is driven LOW with zero delay

and the output is still limited by its turn on delay and the falling edge
slew rate. The output falling edge slew rate is a function of the
internal maximum slew rate which is a function of temperature, V

and process, as well as the load current and the load capacitance.

Rise Time Accelerators

During positive bus transitions a 2 mA current source is switched on
to quickly slew the SDA and SCL lines HIGH once the input level of
0.8 V for the PCA9513 and PCA9514 are exceeded. The rising edge
rate should be at least 1.25 V/

s to guarantee turn on of the

accelerators. The 0.8 V threshold of PCA9513 and PCA9514 allows
for larger bounce-or-noise without falsely triggering the rise time
accelerators.

READY Digital Output

This pin provides a digital flag which is LOW when either ENABLE is
LOW or the start-up sequence described earlier in this section has
not been completed. READY goes HIGH when ENABLE is HIGH
and start-up is complete. The pin is driven by an open drain
pull-down capable of sinking 3 mA while holding 0.4 V on the pin.
Connect a resistor of 10 k

to V

to provide the pull-up.

ENABLE Low Current Disable

Grounding the ENABLE pin disconnects the backplane side from the
card side, disables the rise-time accelerators, drives READY LOW,
disables the bus precharge circuitry, and puts the part in a LOW
current state. When the pin voltage is driven all the way to V

, the

part waits for data transactions on both the backplane and card
sides to be complete before reconnecting the two sides.

Resistor Pull-up Value Selection

The system pull-up resistors must be strong enough to provide a
positive slew rate of 1.25 V/

s on the SDA and SCL pins, in order to

activate the boost pull-up currents during rising edges. Choose
maximum resistor value using the formula:

R v 800 @ 10

CC(MIN)

* 0.6

where R is the pull-up resistor value in

, V

CC(MIN)

is the

minimum V

voltage in volts and C is the equivalent bus

capacitance in picofarads (pF).

In addition, regardless of the bus capacitance, always choose R

16 k

for V

= 5.5 V maximum, R

24 k

for V

= 3.6 V

maximum. The start-up circuitry requires logic high voltages on
SDAOUT and SCLOUT to connect the backplane to the card, and
these pull-up values are needed to overcome the precharge voltage
(PCA9511 only). See the curves in Figures 7 and 8 for guidance in
resistor pull-up selection.

100

200

300

400

BUS

(pF)

PULLUP

)

RECOMMENDED

PULL-UP

MAX

= 24 k

RISE-TIME > 300 ns

SW02115

Figure 7. Bus requirements for 3.3 V systems

100

200

300

400

BUS

(pF)

PULLUP

)

RECOMMENDED

PULL-UP

MAX

= 16 k

RISE-TIME

> 300 ns

SW02116

Figure 8. Bus requirements for 5 V systems

Minimum SDA and SCL Capacitance Requirements

The device connection circuitry requires a minimum capacitance
loading on the SDA and SCL pins in order to function properly. The
value of this capacitance is a function of V

and the bus pull-up

resistance. Estimate the bus capacitance on both the backplane and
the card data and clock buses, and refer to Figures 7 and 8 to
choose appropriate pull-up resistor values. Note from the figures
that 5 V systems should have at least 47 pF capacitance on their
buses and 3.3 V systems should have at least 22 pF capacitance for
proper operation. Although the device has been designed to be
marginally stable with smaller capacitance loads, for applications
with less capacitance, provisions need to be made to add a
capacitor to ground to ensure these minimum capacitance
conditions if oscillations are noticed during initial signal integrity
verification.

Philips Semiconductors

Product data sheet

PCA9513; PCA9514

Hot swappable I

C and SMBus bus buffer

2004 Oct 05

Hot Swapping and Capacitance Buffering
Application

Figures 9 through 12 illustrate the usage of the PCA9513 and
PCA9514 in applications that take advantage of both its hot
swapping and capacitance buffering features. In all of these
applications, note that if the I/O cards were plugged directly into the
backplane, all of the backplane and card capacitances would add
directly together, making rise- and fall-time requirements difficult to

meet. Placing a bus buffer on the edge of each card, however,
isolates the card capacitance from the backplane. For a given I/O
card, the PCA9513 or PCA9514 drives the capacitance of
everything on the card and the backplane must drive only the the
capacitance of the bus buffer, which is less than 10 pF, the
connector, trace, and all additional cards on the backplane.

See Application Note

AN10160, Hot Swap Bus Buffer for more

information on applications and technical assistance.

0.01

10 k

POWER SUPPLY

HOT SWAP

I/O PERIPHERAL CARD 1

10 k

ENABLE

SDAIN

SCLIN

SDAOUT

SCLOUT

READY

GND

CARD1_SDA

CARD1_SCL

10 k

R2
10 k

SDA

SCL

BD_SEL

BACKPLANE

CONNECTOR

0.01

10 k

POWER SUPPLY

HOT SWAP

I/O PERIPHERAL CARD 2

R10

10 k

ENABLE

SDAIN

SCLIN

SDAOUT

SCLOUT

GND

CARD2_SDA

CARD2_SCL

0.01

R12

10 k

R13

10 k

POWER SUPPLY

HOT SWAP

I/O PERIPHERAL CARD N

R14

10 k

ENABLE

SDAIN

SCLIN

SDAOUT

SCLOUT

GND

CARDN_SDA

CARDN_SCL

SW02126

R11

10 k

READY

AGGERED CONNECT

Figure 9. Hot swapping multiple I/O cards into a backplane using the PCA9514 in a CompactPCI, VME, and AdvancedTCA system

Philips Semiconductors

Product data sheet

PCA9513; PCA9514

Hot swappable I

C and SMBus bus buffer

2004 Oct 05

ELECTRICAL CHARACTERISTICS

= 2.7 V to 5.5 V; T

amb

= 40 to +85

C unless otherwise noted.

SYMBOL

PARAMETER

TEST CONDITIONS

LIMITS

UNIT

SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Power supply

Supply voltage

Note 1

2.7

5.5

Supply current

= 5.5 V;

SDAIN

= V

SCLIN

= 0 V; Note 1

2.8

CC(sd)

Supply current in shut-down mode

ENABLE

= 0 V, all other pins at

or GND

200

Start-up circuitry

Enable threshold voltage

0.5

0.7

DIS

Disable threshold voltage

0.3

0.5

Enable input current

Enable from 0 V to V

0.1

Enable delay or initialization time

130

IDLE

Bus idle time

Note 1

140

250

DIS

Disable time, ENABLE to Ready

STOP

SDAIN to READY delay after STOP

Note 7

1.3

READY

SCLOUT/SDAOUT to READY

Note 7

1.2

OFF

Ready off state leakage current

= V

0.3

ENABLE capacitance

= V

or GND; Note 4

Ready capacitance

= V

or GND; Note 4

OL(READY)

LOW-level output voltage on
READY pin

pull-up

= 3 mA; V

= V

CC;

Note 1.

0.4

Rise time accelerators

PULLUPAC

Transient boosted pull-up current

Positive transition on SDA, SCL,
V

= 2.7 V;

Slew rate = 1.25 V/

s; Note 2

Inputoutput connection

Inputoutput offset voltage

10 k

to V

on SDA, SCL;

= 3.3 V; Note 1; Note 3.

150

SCL_SDA

operating frequency

400

kHz

PLH

SCL to SCL and SDA to SDA

10 k

to V

;

= 100 pF each side

PHL

SCL to SCL and SDA to SDA

10 k

to V

;

= 100 pF each side

380

Digital input capacitance

Note 4

LOW-level output voltage

Input = 0 V;
SDA, SCL pins, I

SINK

= 3 mA;

= 2.7 V; Note 1

0.4

PULLUP

SDAIN/SCLIN pull-up current

ENABLE

CC;

Note 6

100

125

Input leakage current

SDA, SCL pins = V

= 5.5 V

Philips Semiconductors

Product data sheet

PCA9513; PCA9514

Hot swappable I

C and SMBus bus buffer

2004 Oct 05

SYMBOL

UNIT

LIMITS

TEST CONDITIONS

PARAMETER

SYMBOL

UNIT

MAX.

TYP.

MIN.

TEST CONDITIONS

PARAMETER

System characteristics

I2C

C operating frequency

400

kHz

BUF

Bus free time between stop and
start condition

Note 4

1.3

hD,STA

Hold time after (repeated) start
condition

Note 4

0.6

su,STA

Repeated start condition setup time

Note 4

0.6

su,STO

Stop condition setup time

Note 4

0.6

hD,DAT

Data hold time

Note 4

300

su,DAT

Data setup time

Note 4

100

LOW

Clock LOW period

Note 4

1.3

HIGH

Clock HIGH period

Note 4

0.6

Clock, data fall time

Notes 4 and 5

20 + 0.1

300

Clock, data rise time

Notes 4 and 5

20 + 0.1

300

NOTES:
1. This specification applies over the full operating temperature range.
2. I

PULLUPAC

varies with temperature and V

voltage, as shown in the Typical Performance Characteristics section.

3. The connection circuitry always regulates its output to a higher voltage than its input. The magnitude of this offset voltage as a function of the

pull-up resistor and V

voltage is shown in the Typical Performance Characteristics section.

4. Guaranteed by design, not production tested.
5. C

= total capacitance of one bus line in pF.

6. SDAIN/SCLIN = 0.1 V, SDAOUT/SCLOUT through resistor to V

7. Delays that can occur after ENABLE and/or idle times have passed.

Philips Semiconductors

Product data sheet

PCA9513; PCA9514

Hot swappable I

C and SMBus bus buffer

2004 Oct 05

Purchase of Philips I

C components conveys a license under the Philips' I

C patent

to use the components in the I

C system provided the system conforms to the

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Definitions

Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.

Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described
or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.

Contact information

For additional information please visit
http://www.semiconductors.philips.com.

Fax: +31 40 27 24825

For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.

Koninklijke Philips Electronics N.V. 2004

Date of release: 10-04

Document number:

9397 750 14001

Philips
Semiconductors

Data sheet status

[1]

Objective data

Preliminary data

Product data

Product
status

[2] [3]

Development

Qualification

Production

Definitions

This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.

This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.

This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).

Data sheet status

[1] Please consult the most recently issued data sheet before initiating or completing a design.

[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL

http://www.semiconductors.philips.com.

[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.

Level

III

Document Outline

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Document Outline

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