1
IDT54/74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AUGUST 1999
1999 Integrated Device Technology, Inc.
DSC-5430/-
c
IDT54/74FCT162260AT/CT/ET
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FAST CMOS
12-BIT TRI-PORT
BUS EXCHANGER
DESCRIPTION:
The FCT162260AT/CT/ET Tri-Port Bus Exchangers are high-speed
12-bit latched bus multiplexers/transceivers for use in high-speed micropro-
cessor applications. These Bus Exchangers support memory interleaving
with latched outputs on the B ports and address multiplexing with latched
inputs on the B ports.
The Tri-Port Bus Exchanger has three 12-bit ports. Data may be
transferred between the A port and either/both of the B ports. The latch
enable (LE1B, LE2B, LEA1B and LEA2B) inputs control data storage.
When a latch-enable input is high, the latch is transparent. When a latch-
enable input is low, the data at the input is latched and remains latched until
the latch enable input is returned high. Independent output enables (
OE1B
and
OE2B) allow reading from one port while writing to the other port.
The FCT162260AT/CT/ET have balanced output drive with current
limiting resistors. This offers low ground bounce, minimal undershoot, and
controlled output fall times - reducing the need for external series terminating
resistors.
FUNCTIONAL BLOCK DIAGRAM
A-1B
LATCH
LEA1B
LE1B
LE2B
12
M
U
X
12
OE1B
12
A
1:12
1B-A
LATCH
1B
1:12
12
12
12
2B-A
LATCH
12
12
A-2B
LATCH
LEA2B
12
2B
1:12
OE2B
OEA
SEL
1
0
29
30
2
28
1
27
55
56
FEATURES:
-
0.5 MICRON CMOS Technology
-
High-speed, low-power CMOS replacement for ABT functions
-
Typical t
SK
(o) (Output Skew) < 250ps
-
Low input and output leakage
1 A (max.)
-
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
-
25 mil pitch SSOP, 19.6 mil pitch TSSOP,15.7 mil pitch TVSOP and
25 mil pitch CERPACK packages
-
Extended commercial range of -40C to +85C
-
V
CC
= 5V 10%
-
Balanced Output Drivers:
24mA (commercial)
16mA (military)
-
Reduced system switching noise
-
Typical V
OLP
(Output Ground Bounce) < 0.6V at V
CC
= 5V, T
A
=
25C
2
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
SSOP/ TSSOP/ TVSOP/ CERPACK
TOP VIEW
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
Unit
V
TERM(2)
Terminal Voltage with Respect to GND
0.5 to +7
V
V
TERM(3)
Terminal Voltage with Respect to GND
0.5 to V
CC
+0.5
V
T
STG
Storage Temperature
65 to +150
C
I
OUT
DC Output Current
60 to +120
mA
5v16-link
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2. All device
terminals except FCT162XXXT Output and I/O terminals.
3. Output and I/O terminals for FCT162XXXT.
CAPACITANCE (T
A
= +25
O
C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
3.5
6
pF
C
OUT
Output Capacitance
V
OUT
= 0V
3.5
8
pF
5v16-link
NOTE:
1. This parameter is measured at characterization but not tested.
O EA
LE1B
G ND
2B
2
V
C C
A
3
A
6
A
7
G ND
A
1 2
2B
3
2B
1
A
1
A
2
G ND
A
4
A
5
A
8
A
9
A
1 0
V
C C
1B
1
A
1 1
1B
2
LEA2B
2B
4
G ND
2B
5
2B
6
V
C C
2B
7
2B
8
G ND
2B
10
2B
11
2B
12
1B
11
1B
10
G ND
1B
9
V
C C
1B
6
1B
8
2B
9
1B
12
1B
7
1B
5
O E2B
39
29
30
31
32
33
34
35
36
37
38
25
26
27
28
48
47
41
42
43
44
45
46
40
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
SO 56-1
SO 56-2
SO 56-3
E56-1
LE2B
G ND
SEL
1B
3
O E1B
G ND
1B
4
LEA1B
49
56
55
50
51
52
53
54
3
IDT54/74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTION TABLES
(1)
Inputs
Output
1B
2B
SEL
LE1B
LE2B
OEA
A
H
X
H
H
X
L
H
L
X
H
H
X
L
L
X
X
H
L
X
L
A
(1)
X
H
L
X
H
L
H
X
L
L
X
H
L
L
X
X
L
X
L
L
A
(1)
X
X
X
X
X
H
Z
Inputs
Outputs
A
LEA1B LEA2B
OE1B
OE2B
1B
2B
H
H
H
L
L
H
H
L
H
H
L
L
L
L
H
H
L
L
L
H
B
(1)
L
H
L
L
L
L
B
(1)
H
L
H
L
L
B
(1)
H
L
L
H
L
L
B
(1)
L
X
L
L
L
L
B
(1)
B
(1)
X
X
X
H
H
Z
Z
X
X
X
L
H
Active
Z
X
X
X
H
L
Z
Active
X
X
X
L
L
Active
Active
PIN DESCRIPTION
Signal
I/O
Description
A
(1:12)
I/O
Bidirectional Data Port A. Usually connected to the CPU's Address/Data bus.
1B
(1:12)
I/O
Bidirectional Data Port 1B. Connected to the even path or even bank of memory.
2B
(1:12
)
I/O
Bidirectional Data Port 2B. Connected to the odd path or odd bank of memory.
LEA1B
I
Latch Enable Input for A-1B Latch. The Latch is open when LEA1B is HIGH. Data from the A-port is latched on the HIGH to LOW transition
of LEA1B.
LEA2B
I
Latch Enable Input for A-2B Latch. The Latch is open when LEA2B is HIGH. Data from the A-Port is latched on the HIGH to LOW transition
of LEA2B.
LE1B
I
Latch Enable Input for the 1B-A Latch. The Latch is open when LE1B is HIGH. Data from the 1B port is latched on the HIGH to LOW transition
of LE1B.
LE2B
I
Latch Enable Input for the 2B-A Latch. The Latch is open when LE2B is HIGH. Data from the 2B port is latched on the HIGH to LOW transition
of LE2B.
SEL
I
1B or 2B Path Selection. When HIGH, SEL enables data transfer from 1B Port to A Port. When LOW, SEL enables data transfer from 2B Port
to A Port.
OEA
I
Output Enable for A Port (Active LOW).
OE1B
I
Output Enable for 1B Port (Active LOW).
OE2B
I
Output Enable for 2B Port (Active LOW).
NOTES:
1. Output level before the indicated steady-state input conditions were
established.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-Impedance
4
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= -40C to +85C, V
CC
= 5.0V 10%; Military: T
A
= -55C to +125C, V
CC
= 5.0V 10%
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
V
IH
Input HIGH Level
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Level
Guaranteed Logic LOW Level
--
--
0.8
V
I
IH
Input HIGH Current (Input pins)
(5)
V
CC
= Max.
V
I
= V
CC
--
--
1
A
Input HIGH Current (I/O pins)
(5)
--
--
1
I
IL
Input LOW Current (Input pins)
(5)
V
I
= GND
--
--
1
Input LOW Current (I/O pins)
(5)
--
--
1
I
OZH
High Impedance Output Current
V
CC
= Max.
V
O
= 2.7V
--
--
1
A
I
OZL
(3-State Output pins)
(5)
V
O
= 0.5V
--
--
1
V
IK
Clamp Diode Voltage
V
CC
= Min., I
IN
= 18mA
--
0.7
1.2
V
I
OS
Short Circuit Current
V
CC
= Max., V
O
= GND
(3)
80
140
250
mA
V
H
Input Hysteresis
--
--
100
--
mV
I
CCL
I
CCH
I
CCZ
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
--
5
500
A
5v16-link
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
ODL
Output LOW Current
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
60
115
200
mA
I
ODH
Output HIGH Current
V
CC
= 5V, V
IN
= V
IH
or V
IL
, V
O
= 1.5V
(3)
60
115
200
mA
V
OH
Output HIGH Voltage
V
CC
= Min.
I
OH
= 16mA MIL.
2.4
3.3
--
V
V
IN
= V
IH
or V
IL
I
OH
= 24mA COM'L.
V
OL
Output LOW Voltage
V
CC
= Min.
I
OL
= 16mA MIL.
--
0.3
0.55
V
V
IN
= V
IH
or V
IL
I
OL
= 24mA COM'L
5v16-link
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second.
4. Duration of the condition can not exceed one second.
5. The test limit for this parameter is 5A at T
A
= -55C.
OUTPUT DRIVE CHARACTERISTICS
5
IDT54/74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Min.
Typ.
(2)
Max.
Unit
I
CC
Quiescent Power Supply Current
TTL Inputs HIGH
V
CC
= Max.
V
IN
= 3.4V
(3)
--
0.5
1.5
mA
I
CCD
Dynamic Power Supply Current
(4)
V
CC
= Max.
Outputs Open
One Output Port Enabled
LExx = V
CC
One Input Bit Toggling
One Output Bit Toggling
50% Duty Cycle
V
IN
= V
CC
V
IN
= GND
--
60
100
A/
MHz
I
C
Total Power Supply Current
(6)
V
CC
= Max.
Outputs Open
fi = 10MHz
V
IN
= V
CC
V
IN
= GND
--
0.6
1.5
mA
50% Duty Cycle
One Output Port Enabled
LExx = V
CC
One Input Bit Toggling
One Output Bit Toggling
V
IN
= 3.4V
V
IN
= GND
--
0.9
2.3
V
CC
= Max.
Outputs Open
fi = 2.5MHz
V
IN
= V
CC
V
IN
= GND
--
1.8
3.5
(5)
50% Duty Cycle
One Output Port Enabled
LExx = V
CC
Twelve Input Bits Toggling
Twelve Output Bits Toggling
V
IN
= 3.4V
V
IN
= GND
--
4.8
12.5
(5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
I
CC
D
H
N
T
+ I
CCD
(f
CP
N
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current (I
CCL
,
I
CCH
and I
CCZ
)
I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
N
CP
= Number of Clock Inputs at f
CP
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
6
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
FCT162260AT
FCT162260CT
FCT162260ET
Com'l.
Mil.
Com'l.
Mil.
Com'l.
Mil.
Symbol
Parameter
Condition
(1)
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Min
.
(2)
Max
.
Unit
t
PLH
t
PHL
Propagation Delay
Ax to 1Bx or Ax to 2Bx
C
L
= 50pF
R
L
= 500
1.5
5.2
1.5
5.6
1.5
4.7
1.5
5.1
1.5
3.6
--
--
ns
t
PLH
t
PHL
Propagation Delay
1Bx to Ax or 2Bx to Ax
1.5
5.6
1.5
5.9
1.5
5
1.5
5.4
1.5
3.6
--
--
ns
t
PLH
t
PHL
Propagation Delay
LExB to Ax
1.5
5.2
1.5
5.6
1.5
4.7
1.5
5.1
1.5
4
--
--
ns
t
PLH
t
PHL
Propagation Delay
LEA1B to 1Bx or LEA2B to 2Bx
1.5
4.7
1.5
5.2
1.5
4.4
1.5
4.8
1.5
4
--
--
ns
t
PLH
t
PHL
Propagation Delay
SEL to Ax
1.5
5.2
1.5
5.6
1.5
4.7
1.5
5.1
1.5
4
--
--
ns
t
PZH
t
PZL
Output Enable Time
OEA to Ax, OE1B to 1BX, or OE2B to 2Bx
1.5
5.7
1.5
6.1
1.5
5.1
1.5
5.4
1.5
4.4
--
--
ns
t
PHZ
t
PLZ
Output Disable Time
OEA to Ax, OE1B to 1BX, or OE2B to 2Bx
1.5
4.4
1.5
4.8
1.5
4
1.5
4.4
1.5
4
--
--
ns
t
SU
Set-Up Time, HIGH or LOW Data to Latch
1.5
--
1.5
--
1
--
1
--
1
--
--
--
ns
t
H
Hold Time, Latch to Data
1
--
1.5
--
1
--
1.5
--
1
--
--
--
ns
t
W
Pulse Width, Latch HIGH
(4)
3
--
3
--
3
--
3
--
3
--
--
--
ns
t
SK
(o)
Output Skew
(3)
--
0.5
--
0.5
--
0.5
--
0.5
--
0.5
--
--
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
4. This parameter is guaranteed but not tested.
7
IDT54/74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
O UT
50pF
500
500
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHR ONOUS C ONTROL
PRESET
CLEAR
ETC.
SYNCHRONOUS CONT ROL
t
SU
t
H
t
RE M
t
SU
t
H
PRESET
CLEAR
CLOCK ENABLE
ETC.
HIGH-LOW -HIGH
PULSE
LOW -HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAM E PHASE
INPUT TRANSITION
3V
1.5V
0V
1.5V
V
O H
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PH L
t
PH L
V
O L
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SW ITCH
CLOSED
SW ITCH
OPEN
V
O L
0.3V
0.3V
t
PLZ
t
PZL
t
PZH
t
PHZ
3.5V
0V
1.5V
1.5V
ENABLE
DISABLE
V
O H
TEST CIRCUITS AND WAVEFORMS
PROPAGATION DELAY
TEST CIRCUITS FOR ALL OUTPUTS
ENABLE AND DISABLE TIMES
SET-UP, HOLD, AND RELEASE TIMES
PULSE WIDTH
SWITCH POSITION
Test
Switch
Open Drain
Disable Low
Closed
Enable Low
All Other Tests
Open
5v16-link
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
1.0MHz; t
F
2.5ns; t
R
2.5ns.
8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
IDT54/74FCT162260AT/CT/ET
FAST CMOS 12-BIT TRI-PORT BUS EXCHANGER
CORPORATE HEADQUARTERS
for SALES:
2975 Stender Way
800-345-7015 or 408-727-6116
Santa Clara, CA 95054
fax: 408-492-8674
www.idt.com*
*To search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
ORDERING INFORMATION
X
Temperature
Range
IDT
FCT
XX XX
Device
Type
X
Package
X
Process
Blank
B
Commercial
MIL-STD-883, Class B
PV
PA
PF
E
Shrink Small Outline Package (SO56-1)
Thin Shrink Small Outline Package (SO56-2)
Thin Very Small Outline Package (SO56-3)
CERPACK (E56-1)
260AT
260CT
260ET
12-Bit Tri-Port Bus Exchanger
55C to +125C
40C to +85C
54
74
XX X
Family
162
Double-Density, 5 Volt, Balanced Drive
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