DECEMBER 2001
DSC-5318/03
1
2000 Integrated Device Technology, Inc.
A
0
-A
19
Address Inputs
Input
Synchronous
CE
1
, CE
2
,
CE
2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/
W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW
1
,
BW
2
,
BW
3
,
BW
4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/
LD
Advance burst address / Load new address
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
Static
TMS
Test Mode Select
Input
N/A
TDI
Test Data Input
Input
N/A
TCK
Test Clock
Input
N/A
TDO
Test Data Input
Output
N/A
ZZ
Sleep Mode
Input
Synchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input / Output
I/O
Synchronous
V
DD
, V
DDQ
Core Power, I/O Power
Supply
Static
V
SS
Ground
Supply
Static
5318 tbl 01
Pin Description Summary
Features
x
x
x
x
x
512K x 36, 1M x 18 memory configurations
x
x
x
x
x
Supports high performance system speed - 200 MHz
(3.0ns Clock-to-Data Access)
x
x
x
x
x
ZBT
TM
Feature - No dead cycles between write and read
cycles
x
x
x
x
x
Internally synchronized output buffer enable eliminates the
need to control
OE
x
x
x
x
x
Single R/
W (READ/WRITE) control pin
x
x
x
x
x
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
x
x
x
x
x
4-word burst capability (interleaved or linear)
x
x
x
x
x
Individual byte write (
BW
1
-
BW
4
) control (May tie active)
x
x
x
x
x
Three chip enables for simple depth expansion
x
x
x
x
x
2.5V power supply (5%)
x
x
x
x
x
2.5V I/O Supply (V
DDQ
)
x
x
x
x
x
Power down controlled by ZZ input
x
x
x
x
x
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Advance
Information
IDT71T75612
IDT71T75812
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
512K x 36, 1M x 18
2.5V Synchronous ZBTTM SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
Description
The IDT71T75612/812 are 2.5V high-speed 18,874,368-bit
(18 Megabit) synchronous SRAMs. They are designed to eliminate dead
bus cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBT
TM
, or Zero
Bus Turnaround.
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71T75612/812 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable
CEN pin allows operation of the IDT71T75612/812
to be suspended as long as necessary. All synchronous inputs are ignored
when (
CEN) is high and the internal device registers will hold their previous
values.
There are three chip enable pins (
CE
1
, CE
2
,
CE
2
) that allow the
user to deselect the device when desired. If any one of these three is not
asserted when ADV/
LD is low, no new memory operation can be initiated.
However, any pending data transfers (reads or writes) will be completed.
6.42
2
IDT71T75612, IDT71T75812, 512K x 36, 1M x 18, 2.5V Synchronous ZBTTM SRAMs with Advance Information
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range
Pin Definitions
(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol
Pin Function
I/O
Active
Description
A
0
-A
19
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK,
ADV/
LD low, CEN low, and true chip enables.
ADV/
LD
Advance / Load
I
N/A
ADV/
LD is a synchronous input that is used to load the internal registers with new address and control when it is
sampled lo w at the rising edge of clock with the chip selected. When ADV/
LD is low with the chip deselected,
any burst in progress is terminated. When ADV/
LD is sampled high then the internal burst counter is advanced
for any burst that was in progress. The external addresses are ignored when ADV/
LD is sampled high.
R/
W
Read / Write
I
N/A
R/
W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write access
to the memory array. The data bus activity for the current cycle takes place two clock cycles later.
CEN
Clock Enable
I
LOW
Synchronous Clock Enable Input. When
CEN is sampled high, all other synchronous inputs, including clock are
ignored and outputs remain unchanged. The effect of
CEN sampled high on the device outputs is as if the low
to high clock transition did not occur. For normal operation,
CEN must be sampled low at rising edge of clock.
BW
1
-
BW
4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable. On load write cycles
(when R/
W and ADV/LD are sampled low) the appropriate byte write signal (BW
1
-
BW
4
) must be valid. The byte
write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when R/ W is sampled
high. The appropriate byte(s) of data are written into the device two cycles later.
BW
1
-
BW
4
can all be tied low if
always doing write to the entire 36-bit word.
CE
1
,
CE
2
Chip Enables
I
LOW
Synchronous active low chip enable.
CE
1
and
CE
2
are used with CE
2
to enable the IDT71T75612/812 (
CE
1
or
CE
2
sampled high or CE
2
sampled low) and ADV/
LD low at the rising edge of clock, initiates a deselect cycle. The
ZBT
TM
has a two cycle deselect, i.e., the data bus will tri-state two clock cycles after deselect is initiated.
CE
2
Chip Enable
I
HIGH
Synchronous active high chip enable. CE
2
is used with
CE
1
and
CE
2
to enable the chip. CE
2
has inverted polarity
but otherwise identical to
CE
1
and
CE
2
.
CLK
Clock
I
N/A
This is the clock input to the IDT71T75612/812. Except for
OE, all timing references for the device are made with
respect to the rising edge of CLK.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are reg istered and triggered
by the rising edge of CLK.
LBO
Linear Burst Order
I
LOW
Burst order selection input. When
LBO is high the Interleaved burst sequence is selected. When LBO is low the
Linear burst sequence is selected.
LBO is a static input and it must not change during device operation.
OE
Output Enable
I
LOW
Asynchronous output enable.
OE must be low to read data from the 71T75612/812. When OE is high the I/O pins
are in a high-impedance state.
OE does not need to be actively controlled for read and write cycles. In normal
operation,
OE can be tied low.
TMS
Test Mode Select
I
N/A
Gives input command for TAP controller. Sampled o n rising edge of TDK.
TDI
Test Data Input
I
N/A
Serial input of registers placed between TDI and TDO. Sampled o n rising edge of TCK.
TCK
Test Clock
I
N/A
Clock input of TAP controller. Each TAP event is clocked. Test inp uts are captured on rising edge of TCK, while
test outputs are driven from the falling edge of TCK.
TDO
Test Data Output
O
N/A
Serial outout of registers placed between TDI and TDO. This outout is active depending on the state of the TAP
controller.
ZZ
Sleep Mode
I
HIGH
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the IDT71T75612/812 to its
lowest power consumption level. Data retention is guaranteed in Sleep Mode.
V
DD
Power Supply
N/A
N/A
2.5V core power supply.
V
DDQ
Power Supply
N/A
N/A
2.5V I/O Supply.
V
SS
Ground
N/A
N/A
Ground.
5318 tbl 02
Description (cont.)
The data bus will tri-state two cycles after the chip is deselected or a write
is initiated.
The IDT71T75612/812 have an on-chip burst counter. In the burst
mode, the IDT71T75612/812 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the
LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/
LD signal is used to load a new
external address (ADV/
LD = LOW) or increment the internal burst counter
(ADV/
LD = HIGH).
The IDT71T75612/812 SRAMs utilize IDT's latest high-performance
2.5V CMOS process, and are packaged in a JEDEC Standard 14mm x
20mm 100pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid
array (BGA).
6.42
IDT71T75612, IDT71T75812, 512K x 36, 1M x 18, 2.5V Synchronous ZBTTM SRAMs with Advance Information
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range
3
Functional Block Diagram
Clk
D
Q
D
Q
D
Q
Address A [0:18]
Control Logic
Address
Control
DI
DO
In
p
u
t
R
eg
i
s
t
e
r
5318 drw 01
Clock
Data I/O [0:31],
I/O P[1:4]
D
Q
Cl
k
Output Register
Mux
Sel
Gate
OE
CE
1, CE2,
CE
2
R/
W
CEN
ADV/
LD
BW
x
LBO
512Kx36 BIT
MEMORY ARRAY
,,
Clk
D
Q
D
Q
D
Q
Address A [0:19]
Control Logic
Address
Control
DI
DO
In
p
u
t
R
eg
i
s
t
e
r
5318 drw 01b
Clock
Data I/O [0:15],
I/O P[1:2]
D
Q
Cl
k
Output Register
Mux
Sel
Gate
OE
CE
1, CE2,
CE
2
R/
W
CEN
ADV/
LD
BW
x
LBO
1Mx18 BIT
MEMORY ARRAY
,
,
6.42
4
IDT71T75612, IDT71T75812, 512K x 36, 1M x 18, 2.5V Synchronous ZBTTM SRAMs with Advance Information
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range
Recommended Operating
Temperature and Supply Voltage
Pin Configuration 512K x 36
NOTES:
1. Pins 14, 16, and 66 do not have to be connected directly to V
DD
as long as the input voltage is
V
IH
.
2. Pins 38, 39 and 43 will be pulled internally to V
DD
if not actively driven. To disable the TAP controller without interfering with normal
operation, several settings are possible. Pins 38, 39 and 43 could be tied to V
DD
or V
SS
and pin 42 should be left unconnected. Or all JTAG
inputs (TMS, TDI and TCK) pins 38, 39 and 43 could be left unconnected "NC" and the JTAG circuit will remain disabled from power up.
3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin TQFP package for the 36M ZBT device.
Top View
100 TQFP
Recommended DC Operating
Conditions
NOTE:
1. V
IL
(min.) = 0.8V for pulse width less than t
CYC
/2, once per cycle.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Core Supply Voltage
2.375
2.5
2.625
V
V
DDQ
I/O Supply Voltage
2.375
2.5
2.625
V
V
SS
Ground
0
0
0
V
V
IH
Input High Voltage - Inputs
1.7
____
V
DD
+0.3
V
V
IH
Input High Voltage - I/O
1.7
____
V
DDQ
+0.3
V
V
IL
Input Low Voltage
-0.3
(1)
____
0.7
V
5318 tbl 03
Grade
Temperature
(1)
V
SS
V
DD
V
DDQ
Commercial
0C to +70C
0V
2.5V5%
2.5V5%
5318 tbl 05
100 99 98 97 96 95 94 93 92 91 90
87 86 85 84 83 82 81
89 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
C
E
1
C
E
2
B
W
4
B
W
3
B
W
2
B
W
1
C
E
2
V
D
D
V
S
S
C
LK
R
/W
C
E
N
O
E
A
D
V
/L
D
A
18
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
T
C
K
/N
C
(2
,3
)
T
D
O
/N
C
(2
)
T
D
I/N
C
(2
)
T
M
S
/N
C
(2
)
LB
O
A
14
A
13
A
12
A
11
A
10
V
D
D
V
S
S
A
0
A
1
A
2
A
3
A
4
A
5
I/O
31
I/O
30
V
DDQ
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DDQ
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DDQ
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DDQ
I/O
17
I/O
16
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
5318
drw 02
V
DD
(1)
I/O
15
I/O
P3
V
DD
(1)
I/O
P4
A
15
A
16
I/O
P1
V
DD
(1)
I/O
P2
ZZ
A
17
,
NOTE:
1. T
A
is the "instant on" case temperature.
6.42
IDT71T75612, IDT71T75812, 512K x 36, 1M x 18, 2.5V Synchronous ZBTTM SRAMs with Advance Information
2.5V I/O, Burst Counter, and Pipelined Outputs Commercial Temperature Range
5
Absolute Maximum Ratings
(1)
Pin Configuration 1Mx 18
100-Pin TQFP Capacitance
(T
A
= +25C, f = 1.0MHz)
NOTES:
1. Pins 14, 16, and 66 do not have to be connected directly to V
DD
as long as
the input voltage is
V
IH
.
2. Pins 38, 39 and 43 will be pulled internally to V
DD
if not actively driven. To
disable the TAP controller without interfering with normal operation, several
settings are possible. Pins 38, 39 and 43 could be tied to V
DD
or V
SS
and
pin 42 should be left unconnected. Or all JTAG inputs (TMS, TDI and TCK)
pins 38, 39 and 43 could be left unconnected "NC" and the JTAG circuit
will remain disabled from power up.
3. Pin 43 is reserved for the 36M address. JTAG is not offered in the 100-pin
TQFP package for the 36M ZBT device.
Top View
100 TQFP
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
DD
terminals only.
3. V
DDQ
terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed V
DDQ
during power
supply ramp up.
7. T
A
is the "instant on" case temperature.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol
Rating
Commercial
Unit
V
TERM
(2)
Terminal Voltage with
Respect to GND
-0.5 to +3.6
V
V
TERM
(3,6)
Terminal Voltage with
Respect to GND
-0.5 to V
DD
V
V
TERM
(4,6)
Terminal Voltage with
Respect to GND
-0.5 to V
DD
+0.5
V
V
TERM
(5,6)
Terminal Voltage with
Respect to GND
-0.5 to V
DDQ
+0.5
V
T
A
(7)
Operating Temperature
0 to +70
o
C
T
BIAS
Temperature Under Bias
-55 to +125
o
C
T
STG
Storage Temperature
-55 to +125
o
C
P
T
Power Dissipation
2.0
W
I
OUT
DC Output Current
50
mA
5318 tbl 06
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
5
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
7
pF
5318 tbl 07
100 99 98 97 96 95 94 93 92 91 90
87 86 85 84 83 82 81
89 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
C
E
1
C
E
2
N
C
N
C
B
W
2
B
W
1
C
E
2
V
D
D
V
S
S
C
LK
R
/W
C
E
N
O
E
A
D
V
/L
D
A
19
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LB
O
A
15
A
14
A
13
A
12
A
11
V
D
D
V
S
S
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
V
DDQ
V
SS
NC
I/O
P2
I/O
15
I/O
14
V
SS
V
DDQ
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
V
DDQ
V
SS
I/O
9
I/O
8
NC
NC
V
SS
V
DDQ
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
DD
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
5318 drw 02a
V
DD
(1)
NC
NC
V
DD
(1)
NC
A
16
A
17
NC
V
DD
(1)
A
10
ZZ
A
18
,
T
C
K
/N
C
(2
,
3
)
T
D
O
/N
C
(2
)
T
D
I/
N
C
(2
)
T
M
S
/N
C
(2
)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
7
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
7
pF
5318 tbl 07a
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
TDB
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
TDB
pF
5318 tbl 07b
165 fBGA Capacitance
(T
A
= +25C, f = 1.0MHz)
119 BGA Capacitance
(T
A
= +25C, f = 1.0MHz)
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