1
INDUSTRIAL TEMPERATURE RANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
R
D
Q
Q
0
R
D
Q
Q
1
R
D
Q
Q
2
R
D
Q
Q
3
R
D
Q
Q
4
R
D
Q
Q /2
0
1
1
0
/2
VCO
LOO P
FILTER
PH AS E
D ETE CTO R
FREQ _SEL
FEED BACK
SYNC
PLL_EN
O E/RST
Q
SEPTEMBER 2000
2000 Integrated Device Technology, Inc.
DSC-5849
c
QS5930T
INDUSTRIAL TEMPERATURE RANGE
LOW SKEW CMOS PLL
CLOCK DRIVER WITH
INTEGRATED LOOP FILTER
FUNCTIONAL BLOCK DIAGRAM
FEATURES:
5V operation
Q/2 output, 5 Q outputs
Useful for Pentium, PowerPC, and PCI systems
Internal loop filter RC network
Low noise TTL level outputs
<250ps rising edge output skew
Balanced drive outputs 24mA
PLL bypass feature for low frequency testing
Internal VCO/2 option for wider frequency range
Outputs tri-state and reset while OE/RST is low
ESD > 2000V
Latch up > -300mA
Available in QSOP package
DESCRIPTION
The QS5930T Clock Driver uses an internal phase locked loop
(PLL) to lock low skew outputs to a reference clock input. Six outputs
are available: Q
0
Q
4
, Q/2. Careful layout and design ensure < 250ps
skew between the Q
0
Q
4
, and Q/2 outputs. The QS5930T includes
an internal RC filter which provides excellent jitter characteristics and
eliminates the need for external components. Various combinations of
feedback and a divide-by-2 in the VCO path allow applications to be
customized for linear VCO operation over a wide range of input SYNC
frequencies. The PLL can also be disabled by the PLL_EN signal to
allow low frequency or DC testing. The QS5930T is designed for use
in cost sensitive high-performance computing systems, workstations,
multi-board computers, networking hardware, and mainframe sys-
tems. Several can be used in parallel or scattered throughout a sys-
tem for guaranteed low skew, system-wide clock distribution networks.
In the QSOP package, the QS5930T clock driver represents the best
value in small form factor, high-performance clock management prod-
ucts.
For more information on PLL clock driver products, see Application
Note AN-227.
2
INDUSTRIAL TEMPERATURE RANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
PIN CONFIGURATION
QSOP
TOP VIEW
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND
OE/RST
FEEDBACK
AV
DD
AGND
SYNC
FREQ_SEL
GND
Q
0
Q
4
Q/2
GND
Q
3
Q
2
GND
PLL_EN
GND
Q
1
V
DD
V
DD
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Rating
Max.
Unit
AV
DD
,V
DD
Supply Voltage to Ground
0.5 to +7
V
DC Input Voltage V
IN
0.5 to +7
V
AC Input Voltage (for pulse width
20ns)
3
V
Maximum Power Dissipation (T
A
= 85C)
1
W
T
STG
Storage Temperature Range
65 to +150
C
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
CAPACITANCE
(T
A
= 25
C, f = 1MHz, V
IN
= 0V)
Pins
Typ.
Max.
Unit
C
IN
3
4
pF
C
OUT
7
9
pF
PIN DESCRIPTION
Pin Name
I/O
Description
SYNC
I
Reference clock input
FREQ_SEL
I
VCO frequency select. For choosing optimal VCO operating frequency depending on input frequency. HIGH is for higher
frequencies, LOW is for lower frequencies.
FEEDBACK
I
PLL feedback input which is connected to either a Q or a Q/2 output. External feedback provides flexibility for different output
frequency relationships. See the Frequency Selection Table for more information.
Q
0
-Q
4
O
Clock outputs
Q/2
O
Clock output. Matched in phase, but frequency is half the Q frequency.
OE/RST
I
Output enable/asynchronous reset. Resets all output registers. When 0, all outputs are held in a tri-stated condition. When 1,
outputs are enabled.
PLL_EN
I
PLL enable. Enables and disables the PLL. Allows the SYNC input to be single-stepped for system debug.
V
DD
--
Power supply for output buffers.
AV
DD
--
Power supply for phase lock loop and other internal circuitries.
GND
--
Ground supply for output buffers.
AGND
--
Ground supply for phase lock loop and other internal circuitries.
OUTPUT FREQUENCY SPECIFICATIONS
Industrial: T
A
= 40C to +85C, AV
DD
/V
DD
= 5V 10%
Symbol
Description
50
66
Units
F
MAX_Q
Max Frequency, Q
0
- Q
4
,
50
66
MHz
F
MAX_Q/2
Max Frequency, Q/2
25
33
MHz
F
MIN_Q
Min Frequency, Q
0
- Q
4
28
28
MHz
F
MIN_Q/2
Min Frequency, Q/2
14
14
MHz
3
INDUSTRIAL TEMPERATURE RANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
NOTE:
1. Operation in the specified SYNC frequency range guarantees that the VCO will operate in its optimal range of 28MHz to F
MAX_Q
x2. Operation with
Sync inputs outside specified frequency ranges may result in out-of-lock outputs. FREQ_SEL only affects VCO frequency and does not affect output
frequencies.
FREQUENCY SELECTION TABLE
Output Used for
SYNC (MHz)
(allowable range)
(1)
Output Frequency Relationships
FREQ_SEL
Feedback
Min.
Max
Q/2
Q
0
- Q
4
HIGH
Q/2
14
F
MAX _Q/2
SYNC
SYNC X 2
HIGH
Q
0
-Q
4
28
F
MAX _Q
SYNC / 2
SYNC
LOW
Q/2
7
F
MAX _Q/2
/2
SYNC
SYNC X 2
LOW
Q
0
-Q
4
14
F
MAX _Q
/2
SYNC / 2
SYNC
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= 40C to +85C, AV
DD
/V
DD
= 5V 5%
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH Level
2
--
--
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW Level
--
--
0.8
V
V
OH
Output HIGH Voltage
I
OH
=
-24mA
2.4
--
--
V
I
OH
=
-100A
3
--
--
V
V
OL
Output LOW Voltage
V
DD
= Min., I
OL
= 24mA
--
--
0.55
V
V
DD
= Min., I
OL
= 100
A
--
--
0.2
V
I
OZ
Output Leakage Current
V
OUT
= V
DD
or GND,
V
DD
= Max., Outputs Disabled
--
--
5
A
I
IN
Input Leakage Current
AV
DD
= Max., V
IN
= AV
DD
or GND
--
--
5
A
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
Typ.
Max.
Unit
I
DDQ
Quiescent Power Supply Current
V
DD
= Max., OE/RST = LOW,
SYNC = LOW, All outputs unloaded
--
1
mA
I
DD
Power Supply Current per Input HIGH
V
DD
= Max., V
IN
= 3V
1
30
A
I
DDD
Dynamic Power Supply Current
V
DD
= Max., C
L
= 0pF
0.2
0.3
mA/MHz
INPUT TIMING REQUIREMENTS
Symbol
Description
(1)
Min.
Max.
Unit
t
R
, t
F
Maximum input rise and fall times, 0.8V to 2V
--
3
ns
F
I
Input Clock Frequency, SYNC
(1)
7
F
MAX _Q
MHz
t
PWC
Input clock pulse, HIGH or LOW
(2)
2
--
ns
D
H
Duty Cycle, SYNC
(2)
25
75
%
NOTES:
1. See Output Frequency and Frequency Selection tables for more detail on allowable SYNC input frequencies for different speed grades with
different FEEDBACK and FREQ_SEL combinations.
2. Where pulse witdh implied by D
H
is less than t
WPC
limit, t
WPC
limit applies
4
INDUSTRIAL TEMPERATURE RANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
NOTES:
1. See Test Loads and Waveforms for test load and termination.
2. Skew specifications apply under identical environments (loading, temperature, V
DD
, device speed grade).
3. Measured in open loop mode PLL_EN = 0.
4. Jitter is characterized with Q output at 20MHz. See Frequency Selection Table for information on proper FREQ_SEL level for specified input
frequencies.
5. t
PD
measured at device inputs at 1.5V, Q output at 28MHz.
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
(1)
Min.
Max.
Unit
t
SKR
Output Skew Between Rising Edges, Q
0
-Q
4
(and Q/2)
(2)
--
250
ps
t
SKF
Output Skew Between Falling Edges, Q
0
-Q
4
(and Q/2)
(2)
--
350
ps
t
PW
Pulse Width, Q
0
-Q
4
, Q/2 outputs, 80MHz
T
CY
/2
- 0.5
T
CY
/2 + 0.5
ns
t
J
Cycle-to-Cycle Jitter, F
I
> 33MHz
( 4)
--
250
ns
t
PD
SYNC Input to Feedback Delay
( 5)
- 100
+400
ps
t
PZH
t
PZL
Output Enable Time, OE/RST LOW to HIGH
( 3)
0
7
ns
t
PHZ
t
PLZ
Output Disable Time, OE/RST HIGH to LOW
( 3)
0
6
ns
t
R,
t
F
Output Rise/Fall Times, 0.8V to 2V
0.4
1.5
ns
5
INDUSTRIAL TEMPERATURE RANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
300
30p F
300
7.0V
O U TP U T
V
D D
O U TP U T
160
68
28p F
AC TEST LOADS AND WAVEFORMS
TEST CIRCUIT 1
TEST CIRCUIT 2
SIMPLIFIED DIAGRAM OF QS5930T FEEDBACK
Q /2
Q
VCO /2
/2
PHAS E
DETECTO R
INPU T
PLL OPERATION
The Phase Locked Loop (PLL) circuit included in the QS5930T
provides for replication of incoming SYNC clock signals. Any manipu-
lation of that signal, such as frequency multiplying, is performed by
digital logic following the PLL (see the block diagram). The key advan-
The phase difference between the output and the input frequencies
feeds the VCO which drives the outputs. Whichever output is fed back,
it will stabilize at the same frequency as the input. Hence, this is a true
negative feedback closed loop system. In most applications, the output
will optimally have zero phase shift with respect to the input. In fact, the
internal loop filter on the QS5930T typically provides within 150ps of
phase shift between input and output.
tage of the PLL circuit is to provide an effective zero propagation delay
between the output and input signals. In fact, adding delay circuits in
the feedback path, `propagation delay' can even be negative! A simpli-
fied schematic of the QS5930T PLL circuit is shown below:
If the user wishes to vary the phase difference (typically to compen-
sate for backplane delays), this is most easily accomplished by adding
delay circuits to the feedback path. The respective output used for
feedback will be advanced by the amount of delay in the feedback
path. All other outputs will retain their proper relationships to that output.
6
INDUSTRIAL TEMPERATURE RANGE
QS5930T
LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER
ORDERING INFORMATION
QS
XX
Speed
5930
Low Skew CMOS PLL Clock Driver
with Integrated Loop Filter
XXXX
Device Type
X
Package
Q
Quarter Size Outline Package
-50T
-66T
50MHz. max. frequency
66MHz. max. frequency
X
Process
Blank
Industrial (-40C to +85C)
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
logichelp@idt.com
Santa Clara, CA 95054
fax: 408-492-8674
(408) 654-6459
www.idt.com
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