FOA4100/5100
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N e v e r s t o p t h i n k i n g .
Features
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Compliant to the Optical
Internetworking Forum
(OIF)-Physical Layer Group's
OIF99.102 recommendation
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Jitter performance compliant
with ITU-T and Bellcore
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Internal low phase noise
LC-VCO
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Differential input voltage
range: 40 mV - 800 mV
(pk-pk)
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Two reference clock options:
155 MHz or 622 MHz
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MUX only: Two receiver clock
modes, 311 MHz or 622 MHz
s
Adjustment of sampling
threshold and phase
s
Loss of lock detection
s
Tunable center frequency
from 9.95 GHz to 10.7 GHz
Typical Applications
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Fiber optics telecom and
datacom applications
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SONET/SDH OC-192/STM-64
with and without FEC
Main Advantages
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Data rate from 9.95 Gbit/s
to 10.7 Gbit/s
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Single supply voltage 3.3 V
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Industry's lowest power
consumption of typical 2.5 W
for MUX and DEMUX Chipset
(1.2 W for MUX;
1.3 W for DEMUX)
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Real differential LVDS
interface
(100
termination on-chip)
s
MUX only: advanced FIFO
architecture (2.4 ns drift
tolerance at 9.95 Gbit/s)
F O A 4 1 0 0 / 5 1 0 0
M U X / D E M U X
9 . 9 5 - 1 0 . 7 G b i t / s , 3 . 3 V
S e m i c o n d u c t o r S o l u t i o n s f o r
H i g h S p e e d C o m m u n i c a t i o n
a n d F i b e r O p t i c A p p l i c a t i o n s
FOA41001B1 16:1
Multiplexer with Clock Multiplication Unit Chip
MUX 9.95 - 10.7 Gbit/s, 3.3 V
FOA51001B1 1:16
Demultiplexer with Clock and Data Recovery Chip
DEMUX 9.95 - 10.7 Gbit/s, 3.3 V
The transceiver chipset (MUX + DEMUX) is compliant with the
Optical Internetworking Forum (OIF)-Physical Layer Group's
OIF99.102 recommendation. These devices offer differential inter-
faces at 622 Mbit/s without external components. The multiplexer
integrates a low noise LC VCO, meets Bellcore's OC-192 jitter
requirements and incorporates pseudo 8-Bit FIFO (First in, First out).
The companion FOA51001B1 10 Gbit/s 1:16 demultiplexer encom-
passes a complete CDR with high data system sensitivity to enhance
the system margin. Each device runs on a single 3.3 V power supply,
with consumption of approximately 1.25 W and incorporates an
integrated low noise Phase Locked Loop (PLL).
Packing
Type
MUX 16:1
MUX 16:1
Sales Code
FOA41001B1
FOA41002B1
Package
P-HBGA-92
Bare Die
DEMUX 1:16
DEMUX 1:16
FOA51001B1
FOA51002B1
P-HBGA-92
Bare Die
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Published by Infineon Technologies AG
How to reach us:
http://www.infineon.com
Published by
Infineon Technologies AG,
St.-Martin-Strasse 53,
81541 Mnchen
Infineon Technologies AG 2002. All Rights Reserved.
Attention please!
The information herein is given to describe certain components
and shall not be considered as warranted characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not
limited to warranties of non-infringement, regarding circuits,
descriptions and charts stated herein.
Infineon Technologies is an approved CECC manufacturer.
Information
For further information on technology, delivery terms
and conditions and prices please contact your nearest
Infineon Technologies Office in Germany or our
Infineon Technologies Representatives worldwide.
Warnings
Due to technical requirements components may contain dan-
gerous substances. For information on the types in question
please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-
support devices or systems with the express written approval
of Infineon Technologies, if a failure of such components can
reasonably be expected to cause the failure of that life-sup-
port device or system, or to affect the safety or effectiveness
of that device or system. Life support devices or systems are
intended to be implanted in the human body, or to support
and/or maintain and sustain and/or protect human life. If
they fail, it is reasonable to assume that the health of the user
or other persons may be endangered.
FOA41001B1 MUX Block Diagram
M U X
F I F O
TXCLK_SRC
C M U
0.622
9.95
ERR
TXCLK
REFCLK
TTL TTL TTL TTL Analog Analog Analog
LPCML2
Analog
TTL
LVDS2
CML2
TTL
TTL
PECL2
LVDS2
LVDS2
LVDS2
LVDS2
LVDS2
LVDS2
TTL
TTL TTL
TTL
Analog
Analog
TIA
FOA11002A1
Optional Serial CDR
CDR
FOA31002B1
PIN
1)
DEMUX+CDR
FOA51001B1
Data
Processing
Laser Driver
FOA21002A1
MUX+CMU
FOA41001B1
Laser
1)
Framer/
Mapper
FOAxxxx
One Chip
Transceiver
FOA6100xB1
10 Gbit/s Chipset Overview
Ordering No. B168-H7715-G1-X-7600
Printed in Germany
PS 1201.5
NB
Analog
TTL
TTL
Analog Analog
D E M U X
C D R
DATA_RT
TTL
DATA
FWD
Analog
Analog
CLK
9.95
CLK
0.622
PECL2
TTL
TTL
TTL
TTL
TTL
M U X
0
1
S
Analog
Analog
CML2
LOS
LF1 LF2 ERR
LVDS2
LVDS2
LVDS2
LVDS2
LVDS2
TTL
&
FOA51001B1 DEMUX Block Diagram
PDF 
ZIP