Document Outline

• Cover Page
• Imprint
• We Listen to Your Comments
• Revision History
• Table of Contents
• List of Tables
• List of Figures
• 1 Overview
  • 1.1 Features
    • Table 1 High Performance DDR2-667
    • Table 2 High Performance for DDR2-400B and DDR2-533C
  • 1.2 Description
  • 1.3 Ordering Information
    • Table 3 Ordering Information for RoHS compliant products
• 2 Pin Configuration and Block Diagrams
  • Table 4 Pin Configuration of DDR2 SDRAM
  • Table 5 Abbreviations for Pin Type
  • Table 6 Abbreviations for Buffer Type
  • 2.1 TFBGA Ball Out Diagrams
    • Figure 1 Pin Configuration for x4 components, PG-TFBGA-60 (top view)
    • Figure 2 Pin Configuration for x8 components, PG-TFBGA-60 (top view)
    • Figure 3 Pin Configuration for x16 components, PG-TFBGA-84 (top view)
  • 2.2 512 Mbit DDR2 Addressing
    • Table 7 512 Mbit DDR2 Addressing
  • 2.3 Block Diagrams
    • Figure 4 Block Diagram 32 Mbit x 4 I/O x4 Internal Memory Banks
    • Figure 5 Block Diagram 16 Mbit x 8 I/O x4 Internal Memory Banks
    • Figure 6 Block Diagram 8 Mbit x 16 I/O x4 Internal Memory Banks
• 3 Functional Description
  • 3.1 Simplified State Diagram
    • Figure 7 Simplified State Diagram
  • 3.2 Basic Functionality
  • 3.3 Power On and Initialization
    • Power-up and Initialization Sequence
      • Figure 8 Initialization Sequence after Power up
  • 3.4 Programming the Mode Register and Extended Mode Registers
  • 3.5 DDR2 SDRAM Mode Register Set (MRS)
    • Table 8 Mode Register Definition (BA[2:0] = 000B)
  • 3.6 DDR2 SDRAM Extended Mode Register Set (MRS)
    • Table 9 Extended Mode Register Definition (BA[2:0] = 001B)
  • 3.7 DLL Enable/Disable
  • 3.8 Output Disable (Qoff)
  • 3.9 Single-ended and Differential Data Strobe Signals
    • Table 10 Single-ended and Differential Data Strobe Signals
  • 3.10 Extended Mode Register EMR(2)
    • Table 11 EMRS(2) Programming Extended Mode register Definition (BA[2:0]=010B)
  • 3.11 Extended Mode Register EMR(3)
    • Table 12 EMR(3) Programming Extended Mode Register Definition (BA[2:0]=010B)
  • 3.12 Off-Chip Driver (OCD) Impedance Adjustment
    • OCD Impedance Adjustment Flow Chart
      • Figure 9 OCD Impedance Adjustment Flow Chart
    • Extended Mode Register Set for OCD impedance adjustment
      • Table 13 Off Chip Driver Program
    • OCD impedance adjust
      • Table 14 Off-Chip-Driver Adjust Program
      • Figure 10 Timing Diagram Adjust Mode
    • Drive Mode
      • Figure 11 Timing Diagram Drive Mode
  • 3.13 On-Die Termination (ODT)
    • Figure 12 Functional Representation of ODT
    • ODT Truth Tables
      • Table 15 ODT Truth Table
    • ODT timing modes
      • Figure 13 ODT Timing for Active and Standby (Idle) Modes (Synchronous ODT timings)
      • Figure 14 ODT Timing for Precharge Power-Down and Active Power-Down Mode
    • ODT timing mode switch
    • Mode entry
      • Figure 15 ODT Mode Entry Timing Diagram
    • Mode exit
      • Figure 16 ODT Mode Exit Timing Diagram
  • 3.14 Bank Activate Command
    • Figure 17 Bank Activate Command Cycle
  • 3.15 Read and Write Commands and Access Modes
    • Figure 18 Read Timing Example
  • 3.16 Posted CAS
    • Figure 19 Activate to Read Timing Example: Read followed by a write to the same bank
    • Figure 20 Read to Write Timing Example: Read followed by a write to the same bank
    • Figure 21 Read to Write Timing Example: Read followed by a write to the same bank
    • Figure 22 Read to Write Timing Example: Read followed by a write to the same bank
    • Figure 23 Write to Read Timing Example: Write followed by a read to the same bank
  • 3.17 Burst Mode Operation
    • Table 16 Burst Length and Sequence
  • 3.18 Read Command
    • Figure 24 Basic Read Timing Diagram
    • Figure 25 Read Operation Example 1
    • Figure 26 Read Operation Example 2
    • Figure 27 Read followed by Write Example
    • Figure 28 Seamless Read Operation Example 1
    • Figure 29 Seamless Read Operation Example 2
  • 3.19 Write Command
    • Figure 30 Basic Write Timing
    • Figure 31 Write Operation Example 1
    • Figure 32 Write Operation Example 2
    • Figure 33 Write followed by Read Example
    • Figure 34 Seamless Write Operation Example 1
    • Figure 35 Seamless Write Operation Example 2
  • 3.20 Write Data Mask
    • Figure 36 Write Data Mask Timing
    • Figure 37 Write Operation with Data Mask Example
  • 3.21 Burst Interruption
    • Figure 38 Read Interrupt Timing Example 1
    • Figure 39 Write Interrupt Timing Example 2
  • 3.22 Precharge Command
    • Table 17 Bank Selection for Precharge by Address Bits
    • 3.22.1 Read Followed by a Precharge
      • Figure 40 Read Operation Followed by Precharge Example 1
      • Figure 41 Read Operation Followed by Precharge Example 2
      • Figure 42 Read Operation Followed by Precharge Example 3
      • Figure 43 Read Operation Followed by Precharge Example 4
      • Figure 44 Read Operation Followed by Precharge Example 5
    • 3.22.2 Write followed by Precharge
      • Figure 45 Write followed by Precharge Example 1
      • Figure 46 Write followed by Precharge Example 2
  • 3.23 Auto-Precharge Operation
    • 3.23.1 Read with Auto-Precharge
      • Figure 47 Read with Auto-Precharge Example 1, followed by an Activation to the Same Bank (tRC Limit)
      • Figure 48 Read with Auto-Precharge Example 2, followed by an Activation to the Same Bank (tRAS Limit)
      • Figure 49 Read with Auto-Precharge Example 3, followed by an Activation to the Same Bank
      • Figure 50 Read with Auto-Precharge Example 4, followed by an Activation to the Same Bank,
    • 3.23.2 Write with Auto-Precharge
      • Figure 51 Write with Auto-Precharge Example 1 (tRC Limit)
      • Figure 52 Write with Auto-Precharge Example 2 (WR + tRP Limit)
    • 3.23.3 Read or Write to Precharge Command Spacing Summary
      • Table 18 Minimum Command Delays
    • 3.23.4 Concurrent Auto-Precharge
      • Table 19 Command Delay Table
  • 3.24 Refresh
    • 3.24.1 Auto-Refresh Command
      • Figure 53 Auto Refresh Timing
    • 3.24.2 Self-Refresh Command
      • Figure 54 Self Refresh Timing
  • 3.25 Power-Down
    • Power-Down Entry
    • Power-Down Exit
      • Figure 55 Active Power-Down Mode Entry and Exit after an Activate Command
      • Figure 56 Active Power-Down Mode Entry and Exit Example after a Read Command
      • Figure 57 Active Power-Down Mode Entry and Exit Example after a Write Command
      • Figure 58 Active Power-Down Mode Entry and Exit Example after a Write Command with AP
      • Figure 59 Precharge Power Down Mode Entry and Exit
      • Figure 60 Auto-Refresh command to Power-Down entry
      • Figure 61 MRS, EMRS command to Power-Down entry
  • 3.26 Other Commands
    • 3.26.1 No Operation Command
    • 3.26.2 Deselect Command
  • 3.27 Input Clock Frequency Change
    • Figure 62 Input Frequency Change Example during Precharge Power-Down mode
  • 3.28 Asynchronous CKE LOW Reset Event
    • Figure 63 Asynchronous Low Reset Event
• 4 Truth tables
  • Table 20 Command Truth Table
  • Table 21 Clock Enable (CKE) Truth Table for Synchronous Transitions
  • Table 22 Data Mask (DM) Truth Table
• 5 AC & DC Operating Conditions
  • 5.1 Absolute Maximum Ratings
    • Table 23 Absolute Maximum Ratings
    • Table 24 DRAM Component Operating Temperature Range
  • 5.2 DC Characteristics
    • Table 25 Recommended DC Operating Conditions (SSTL_18)
    • Table 26 ODT DC Electrical Characteristics
    • Table 27 Input and Output Leakage Currents
  • 5.3 DC & AC Characteristics
    • Table 28 DC & AC Logic Input Levels
    • Table 29 Single-ended AC Input Test Conditions
    • Figure 64 Single-ended AC Input Test Conditions Diagram
    • Table 30 Differential DC and AC Input and Output Logic Levels
    • Figure 65 Differential DC and AC Input and Output Logic Levels Diagram
  • 5.4 Output Buffer Characteristics
    • Table 31 SSTL_18 Output DC Current Drive
    • Table 32 SSTL_18 Output AC Test Conditions
    • Table 33 OCD Default Characteristics
  • 5.5 Full Strength Output V-I Characteristics
    • Table 34 Full Strength Default Pull-up Driver Characteristics
    • Figure 66 Full Strength Default Pull-up Driver Diagram
    • Table 35 Full Strength Default Pull-down Driver Characteristics
    • Figure 67 Full Strength Default Pull-down Driver Diagram
    • 5.5.1 Calibrated Output Driver V-I Characteristics
      • Table 36 Full Strength Calibrated Pull-down Driver Characteristics
      • Table 37 Full Strength Calibrated Pull-up Driver Characteristics
  • 5.6 Reduced Output Drive Characteristics
    • Table 38 Reduced Strength Default Pull-up Driver Characteristics
    • Figure 68 Reduced Strength Default Pull-up Driver Diagram
    • Table 39 Reduced Strength Default Pull-down Driver Characteristics
    • Figure 69 Reduced Strength Default Pull-down Driver Diagram
  • 5.7 Input / Output Capacitance
    • Table 40 Input / Output Capacitance
  • 5.8 Power & Ground Clamp V-I Characteristics
    • Table 41 Power & Ground Clamp V-I Characteristics
  • 5.9 Overshoot and Undershoot Specification
    • Table 42 AC Overshoot / Undershoot Specification for Address and Control Pins
    • Figure 70 AC Overshoot / Undershoot Diagram for Address and Control Pins
    • Table 43 AC Overshoot / Undershoot Specification for Clock, Data, Strobe and Mask Pins
    • Figure 71 AC Overshoot / Undershoot Diagram for Clock, Data, Strobe and Mask Pins
• 6 Currents Measurement Specifications and Conditions
  • Table 44 IDD Measurement Conditions
  • Table 45 Definition for IDD
  • Table 46 IDD Specification for HYB18T512xxxAF(L)
  • 6.1 IDD Test Conditions
    • Table 47 IDD Measurement Test Conditions for DDR2-667C and DDR2-667D
    • Table 48 IDD Measurement Test Condition for DDR2-533C and DDR2-400B
    • 6.1.1 On Die Termination (ODT) Current
      • Table 49 ODT current per terminated input pin
• 7 Electrical Characteristics
  • 7.1 Speed Grade Definitions
    • Table 50 Speed Grade Definition Speed Bins for DDR2-667
    • Table 51 Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400
  • 7.2 AC Timing Parameters
    • Table 52 Timing Parameter by Speed Grade - DDR2-667
    • Table 53 Timing Parameter by Speed Grade - DDR2-533
    • Table 54 Timing Parameter by Speed Grade - DDR2-400
  • 7.3 ODT AC Electrical Characteristics
    • Table 55 ODT AC Electrical Characteristics and Operating Conditions for DDR2-667
    • Table 56 ODT AC Electrical Characteristics and Operating Conditions for DDR2-533 and DDR2-400
• 8 AC Timing Measurement Conditions
  • 8.1 Reference Load for Timing Measurements
    • Figure 72 Reference Load for Timing Measurements
  • 8.2 Slew Rate Measurement Conditions
    • 8.2.1 Output Slew Rate
    • 8.2.2 Input Slew Rate - Differential signals
  • 8.3 Input and Data Setup and Hold Time
    • 8.3.1 Definition for Input Setup (tIS) and Hold Time (tIH)
      • Figure 73 Input Setup and Hold Time
    • 8.3.2 Definition for Data Setup (tDS) and Hold Time (tDH), differential Data Strobes
      • Figure 74 Data Setup and Hold Time (Differential Data Strobes)
    • 8.3.3 Definition Data Setup (tDS1) and Hold Time (tDH1), Single-Ended Data Strobes
      • Figure 75 Data Setup and Hold Time (Single Ended Data Strobes)
    • 8.3.4 Slew Rate Definition for Input and Data Setup and Hold Times
      • Figure 76 Slew Rate Definition Nominal
      • Figure 77 Slew Rate Definition Tangent
    • 8.3.5 Setup (tIS) and Hold (tIH) Time Derating Tables
      • Table 57 Derating Values for Input Setup and Hold Time (DDR2-667)
      • Table 58 Derating Values for Input Setup and Hold Time (DDR2-400 & DDR2-533)
      • Table 59 Derating Values for Data Setup and Hold Time of Differential DQS (DDR2-667)
      • Table 60 Derating Values for Data Setup and Hold Time of Differential DQS (DDR2-400 & -533)
      • Table 61 Derating Values for Data Setup and Hold Time of Single-ended DQS (DDR2-400 & -533)
• 9 Package Dimensions
  • Figure 78 Package Pinout PG-TFBGA-60 (bottom view)
  • Figure 79 Package Pinout PG-TFBGA-84 (bottom view)
• 10 Product Namenclature
  • Table 62 Nomenclature Fields and Examples
  • Table 63 DDR2 Memory Components