INFINEON Technologies
1
2.00
Direct RDRAM
128/144-MBit (256K
16/18
32s)
Overview
The Rambus Direct RDRAM
TM
is a general purpose high-performance memory device suitable for
use in a broad range of applications including computer memory, graphics, video, and any other
application where high bandwidth and low latency are required.
The 128/144-Mbit Direct Rambus DRAMs (RDRAM
) are extremely high-speed CMOS DRAMs
organized as 8M words by 16 or 18 bits. The use of Rambus Signaling Level (RSL) technology
permits 600 MHz to 800 MHz transfer rates while using conventional system and board design
technologies. Direct RDRAM devices are capable of sustained data transfers at 1.25 ns per two
bytes (10 ns per sixteen bytes).
The architecture of the Direct RDRAMs allows the highest sustained bandwidth for multiple,
simultaneous randomly addressed memory transactions. The separate control and data buses with
independent row and column control yield over 95% bus efficiency. The Direct RDRAM's thirty-two
banks support up to four simultaneous transactions.
System oriented features for mobile, graphics and large memory systems include power
management, byte masking, and x18 organization. The two data bits in the x18 organization are
general and can be used for additional storage and bandwidth or for error correction.
Features
Highest sustained bandwidth per DRAM device
1.6 GB/s sustained data transfer rate
Separate control and data buses for maximized efficiency
Separate row and column control buses for easy scheduling and highest performance
32 banks: four transactions can take place simultaneously at full bandwidth data rates
Low latency features
Write buffer to reduce read latency
3 precharge mechanisms for controller flexibility
Interleaved transactions
Advanced power management:
Multiple low power states allows flexibility in power consumption versus time to transition to
active state
Power-down self-refresh
Organization: 1 Kbyte pages and 32 banks, x16/18
x18 organization allows ECC configurations or increased storage/bandwidth
x16 organization for low cost applications
Uses Rambus Signaling Level (RSL) for up to 800 MHz operation
The ODF function is allready implemented in this device and will be described in a later
version of this document
Direct RDRAM
128/144-MBit (256K
16/18
32s)
INFINEON Technologies
2
2.00
Figure 1
Direct RDRAM CSP Package
The 128/144-Mbit Direct RDRAMs are offered in a CSP horizontal package suitable for desktop as
well as low-profile add-in card and mobile applications.
Direct RDRAMs operate from a 2.5 V supply.
Table 1
Key Timing Parameters/Part Numbers
Organization
I/O Freq.
MHz
Trac
Part Number
Normal Package:
8M
18
600
53 ns
HYB25R144180C-653
8M
18
711
45 ns
HYB25R144180C-745
8M
18
800
45 ns
HYB25R144180C-845
8M
18
800
40 ns
HYB25R144180C-840
8M
16
600
53 ns
HYB25R128160C-653
8M
16
711
45 n s
HYB25R128160C-745
8M
16
800
45 ns
HYB25R128160C-845
8M
16
800
40 ns
HYB25R128160C-840
Mirror Package:
8M
18
600
53 ns
HYB25M144180C-653
8M
18
711
45 ns
HYB25M144180C-745
8M
18
800
45 ns
HYB25M144180C-845
8M
18
800
40 ns
HYB25M144180C-840
8M
16
600
53 ns
HYB25M128160C-653
8M
16
711
45 n s
HYB25M128160C-745
8M
16
800
45 ns
HYB25M128160C-845
8M
16
800
40 ns
HYB25M128160C-840
INFINEON Technologies
3
2.00
Direct RDRAM
128/144-MBit (256K
16/18
32s)
Pinouts and Definitions
This tables show the pin assignments of the RDRAM package from the top-side of the package (the
view looking down on the package as it is mounted on the circuit board). The mechanical
dimensions of this package are shown in a later section. Refer to Section "Center-Bonded FBGA
Package" on page 86. Note - pin #1 is at the A1 position. DQA8/DQB8 are used for 144 Mbit only.
They are N.C. for 128Mbit.
Table 2
Normal Package (top view)
Table 3
Mirrored Package (top view)
12
GND
VDD
V
DD
GND
11
10
DQA7
DQA4
CFM
CFMN
RQ5
RQ3
DQB0
DQB4
DQB7
9
GND
V
DD
GND
GNDa
V
DD
GND
V
DD
V
DD
GND
8
CMD
DQA5
DQA2
V
DDa
RQ6
RQ2
DQB1
DQB5
SIO1
7
6
5
SCK
DQA6
DQA1
V
REF
RQ7
RQ1
DQB2
DQB6
SIO0
4
V
CMOS
GND
V
DD
GND
GND
V
DD
GND
GND
V
CMOS
3
DQA8
DQA3
DQA0
CTMN
CTM
RQ4
RQ0
DQB3
DQB8
2
1
GND
V
DD
V
DD
GND
A
B
C
D
E
F
G
H
J
12
GND
VDD
V
DD
GND
11
10
DQA8
DQA3
DQA0
CTMN
CTM
RQ4
RQ0
DQB3
DQB8
9
V
CMOS
GND
V
DD
GND
GND
V
DD
GND
GND
V
CMOS
8
SCK
DQA6
DQA1
V
REF
RQ7
RQ1
DQB2
DQB6
SIO0
7
6
5
CMD
DQA5
DQA2
V
DDa
RQ6
RQ2
DQB1
DQB5
SIO1
4
GND
V
DD
GND
GNDa
V
DD
GND
V
DD
V
DD
GND
3
DQA7
DQA4
CFM
CFMN
RQ5
RQ3
DQB0
DQB4
DQB7
2
1
GND
V
DD
V
DD
GND
A
B
C
D
E
F
G
H
J
Direct RDRAM
128/144-MBit (256K
16/18
32s)
INFINEON Technologies
4
2.00
Table 4
Signal
I/O
Type
# Pins
Edge
# Pins
Center
Description
SIO1,SIO0
I/O
CMOS
1)
1)
All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
2
2
Serial input/output. Pins for reading from and writing to
the control registers using a serial access protocol.
Also used for power management.
CMD
I
CMOS
1)
1
1
Command input. Pins used in conjunction with SIO0
and SIO1 for reading from and writing to the control
registers. Also used for power management.
SCK
I
CMOS
1)
1
1
Serial clock input. Clock source used for reading from
and writing to the control registers.
V
DD
14
6
Supply voltage for the RDRAM core and interface logic.
V
DDa
2
1
Supply voltage for the RDRAM analog circuitry.
V
CMOS
2
2
Supply voltage for CMOS input/output pins.
GND
19
9
Ground reference for RDRAM core and interface.
GNDa
2
1
Ground reference for RDRAM analog circuitry.
DQA8 ... DQA0
I/O
RSL
2)
2)
All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
9
9
Data byte A. Nine pins which carry a byte of read or
write data between the Channel and the RDRAM.
DQA8 is not used by RDRAMs with a x16 organization.
CFM
I
RSL
2)
1
1
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
CFMN
I
RSL
2)
1
1
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Negative polarity
V
REF
1
1
Logic threshold reference voltage for RSL signals
CTMN
I
RSL
2)
1
1
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Negative polarity.
CTM
I
RSL
2)
1
1
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Positive polarity.
RQ7 ... RQ5 or
ROW2 ... ROW0
I
RSL
2)
3
3
Row access control. Three pins containing control and
address information for row accesses.
RQ4 ... RQ0 or
COL4 ... COL0
I
RSL
2)
5
5
Column access control. Five pins containing control
and address information for column accesses.
DQB8 ... DQB0
I/O
RSL
2)
9
9
Data byte B. Nine pins which carry a byte of read or
write data between the Channel and the RDRAM.
DQB8 is not used by RDRAMs with a x16 organization.
Total pin count per package
74
54
INFINEON Technologies
5
2.00
Direct RDRAM
128/144-MBit (256K
16/18
32s)
Figure 2
128/144-MBit Direct RDRAM Block Diagram
SPB04206
1:8 Demux
Packet Decode
ROWA
ROWR
11
5
5
9
TCLK
Control Registers
RCLK
CTM CTMN
RCLK
CFM CFMN
8
Packet Decode
COLC
5
5
COLM
8
6
5
COLX
6
5
5
XOPM DX
XOP Decode
Match
Match
Write
Buffer
Mux
Mux
Column Decode & Mask
Match
Mux
Row Decode
1:8 Demux
RCLK
Power Modes
DEVID
REFR
1:8 Demux
RCLK
Write Buffer
9
Bank 0
SAmp
0
0/1
SAmp
Bank 1
SAmp
1/2
Bank 2
Bank 13
SAmp
13/14
Bank 14
SAmp
14/15
Bank 15
SAmp
15
Bank 16
SAmp
16/17
Bank 17
SAmp
17/18
Bank 18
SAmp
Bank 29
SAmp
29/30
Bank 30
SAmp
30/31
Bank 31
SAmp
31
BX COPS DC
BC
C
MB
MA
R
BR
DR
ROPAV
PRER
ACT
PREX
RD, WR
SAmp
0
SAmp
0/1
SAmp
1/2
SAmp
13/14
SAmp
14/15
SAmp
15
SAmp
16/17
SAmp
17/18
SAmp
16
SAmp
29/30
SAmp
30/31
SAmp
31
9
8:1 Mux
9
9
1:8 Demux
Write Buffer
8:1 Mux
9
9
9
9
9
9
72
72
Sense Amp
32 x 72
32 x 72
32 x 72
DRAM Core
512 x 64 x 144
3
9
DQB8...DQB0
ROW2...ROW0
RQ7...RQ5 or
2
2
RQ4...RQ0 or
COL4...COL0
5
DQA8...DQA0
9
DM
TCLK
RCLK
TCLK
Internal DQB Data Path
Internal DQA Data Path
16
SCK, CMD
SIO0, SIO1
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