INFINEON Technologies
1
2.01
HYS64/72D32000GU / HYS64/72D64020GU
Unbuffered DDR-I SDRAM-Modules
2.5 V 184-pin Unbuffered DDR-I SDRAM Modules
256MB & 512MB Modules
Preliminary Datasheet Rev. 0.99
The HYS64/72Dxx0x0GU are industry standard 184-pin 8-byte Dual in-line Memory Modules
(DIMMs) organized as 32M
64 and 64M
64 for non-parity and 32M x 72 and 64M x 72 for ECC
main memory applications. The memory array is designed with Double Data Rate Synchronous
DRAMs. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial
presence detect based on a serial E
2
PROM device using the 2-pin I
2
C protocol. The first 128 bytes
are programmed with configuration data and the second 128 bytes are available to the customer.
184-pin Unbuffered 8-Byte Dual-In-Line
DDR-I SDRAM non-parity and ECC-Modules
for PC and Server main memory applications
One bank 32M
64, 32M x 72 and two bank
64M x 64, 64M
72 organization
JEDEC standard Double Data Rate
Synchronous DRAMs (DDR-I SDRAM)
Single + 2.5 V (
0.2 V) power supply
Built with 256Mbit DDR-I SDRAMs
organisaed as 32Mb x 8 in 66-Lead TSOPII
package
Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
Auto Refresh (CBR) and Self Refresh
All inputs and outputs SSTL_2 compatible
Serial Presence Detect with E
2
PROM
Jedec standard MO-206a form factor:
133.35 mm
31.75 mm
4.00 mm
Jedec standard reference layout
Gold plated contacts
Performance:
-7
-7.5
-8
Unit
Component Speed Grade
DDR266A DDR266B DDR200
Module Speed Grade
PC2100
PC2100
PC1600
f
CK
Clock Frequency (max.) @ CL = 2.5
143
133
125
MHz
f
CK
Clock Frequency (max.) @ CL = 2
133
100
100
MHz
HYS64/72D32000GU / HYS64/72D64020GU
Unbuffered DDR-I SDRAM-Modules
INFINEON Technologies
2
2.01
Note: All part numbers end with a place code (not shown), designating the silicon-die revision.
Reference information available on request.
Example: HYS 72D32000GU-8-A, indicating Rev.A die are used for SDRAM components.
Ordering Information
Type
Compliance Code
Description
SDRAM
Technology
PC2100 (CL=2):
HYS64D32000GU-7
PC2100-20330-B1
one bank 256 MB DIMM
256 MBit
HYS72D32000GU-7
PC2100-20330-B1
one bank 256 MB ECC-DIMM
256 Mbit
HYS64D64020GU-7
PC2100-20330-A1
two banks 512 MB DIMM
256 MBit
HYS72D64020GU-7
PC2100-20330-A1
two banks 512 MB ECC-DIMM
256 MBit
PC2100 (CL=2.5):
HYS64D32000GU-7.5
PC2100-25330-B1
one bank 256 MB DIMM
256 MBit
HYS72D32000GU-7.5
PC2100-25330-B1
one bank 256 MB ECC-DIMM
256 Mbit
HYS64D64020GU-7.5
PC2100-25330-A1
two banks 512 MB DIMM
256 MBit
HYS72D64020GU-7.5
PC2100-25330-A1
two banks 512 MB ECC-DIMM
256 MBit
PC1600 (CL=2):
HYS64D32000GU-8
PC1600-20220-B1
one bank 256 MB DIMM
256 MBit
HYS72D32000GU-8
PC1600-20220-B1
one bank 256 MB ECC-DIMM
256 Mbit
HYS64D64020GU-8
PC1600-20220-A1
two banks 512 MB DIMM
256 MBit
HYS72D64020GU-8
PC1600-20220-A1
two banks 512 MB ECC-DIMM
256 MBit
HYS64/72D32000GU / HYS64/72D64020GU
Unbuffered DDR-I SDRAM-Modules
INFINEON Technologies
3
2.01
Pin Definitions and Functions
A0 - A12
Address Inputs
S0, S1
Chip Selects
BA0, BA1
Bank Selects
V
DD
Power (+ 2.5 V)
DQ0 - DQ63
Data Input/Output
V
SS
Ground
CB0 - CB7
Check Bits (x72 organization only)
V
DDQ
I/O Driver power supply
RAS
Row Address Strobe
V
DDID
VDD Indentification flag
CAS
Column Address Strobe
V
REF
I/O reference supply
WE
Read/Write Input
V
DDSPD
Serial EEPROM power
supply
CKE0 - CKE1
Clock Enable
SCL
Serial bus clock
DQS0 - DQS8
SDRAM low data strobes
SDA
Serial bus data line
CLK0 - CLK2,
SDRAM clock (positive lines)
SA0 - SA2
slave address select
CLK0 - CLK2
SDRAM clock (negative lines)
NC
no connect
DM0 - DM8
DQS9 - DQS17
SDRAM low data mask/
high data strobes
Address Format
Density Organization Memory
Banks
SDRAMs
# of
SDRAMs
# of row/bank/
columns bits
Refresh Period Interval
256 MB 32M x 64
1
32M x 8
8
13/2/10
8k
64 ms 7.8
s
256 MB 32M x 72
1
32M x 8
9
13/2/10
8k
64 ms 7.8
s
512 MB 64M
64
2
32M x 8
16
13/2/10
8k
64 ms 7.8
s
512 MB 64M
72
2
32M x 8
18
13/2/10
8k
64 ms 7.8
s
HYS64/72D32000GU / HYS64/72D64020GU
Unbuffered DDR-I SDRAM-Modules
INFINEON Technologies
4
2.01
Pin Configuration
Frontside
Frontside
Backside
Backside
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
PIN#
Symbol
1
VREF
48
A0
93
VSS
140
NC / DM8/DQS17
2
DQ0
49
NC / CB2
94
DQ4
141
A10
3
VSS
50
VSS
95
DQ5
142
NC / CB6
4
DQ1
51
NC / CB3
96
VDDQ
143
VDDQ
5
DQS0
52
BA1
97
DM0/DQS9
144
NC / CB7
6
DQ2
KEY
98
DQ6
KEY
7
VDD
53
DQ32
99
DQ7
145
VSS
8
DQ3
54
VDDQ
100
VSS
146
DQ36
9
NC
55
DQ33
101
NC
147
DQ37
10
NC
56
DQS4
102
NC
148
VDD
11
VSS
57
DQ34
103
NC
149
DM4/DQS13
12
DQ8
58
VSS
104
VDDQ
150
DQ38
13
DQ9
59
BA0
105
DQ12
151
DQ39
14
DQS1
60
DQ35
106
DQ13
152
VSS
15
VDDQ
61
DQ40
107
DM1/DQS10
153
DQ44
16
CLK1
62
VDDQ
108
VDD
154
RAS
17
CLK1
63
WE
109
DQ14
155
DQ45
18
VSS
64
DQ41
110
DQ15
156
VDDQ
19
DQ10
65
CAS
111
CKE1
157
S0
20
DQ11
66
VSS
112
VDDQ
158
S1
21
CKE0
67
DQS5
113
NC (BA2)
159
DM5/DQS14
22
VDDQ
68
DQ42
114
DQ20
160
VSS
23
DQ16
69
DQ43
115
A12
161
DQ46
24
DQ17
70
VDD
116
VSS
162
DQ47
25
DQS2
71
NC
117
DQ21
163
NC
26
VSS
72
DQ48
118
A11
164
VDDQ
27
A9
73
DQ49
119
DM2/DQS11
165
DQ52
28
DQ18
74
VSS
120
VDD
166
DQ53
29
A7
75
CLK2
121
DQ22
167
NC (A13)
30
VDDQ
76
CLK2
122
A8
168
VDD
31
DQ19
77
VDDQ
123
DQ23
169
DM6/DQS15
32
A5
78
DQS6
124
VSS
170
DQ54
33
DQ24
79
DQ50
125
A6
171
DQ55
34
VSS
80
DQ51
126
DQ28
172
VDDQ
35
DQ25
81
VSS
127
DQ29
173
NC
36
DQS3
82
VDDID
128
VDDQ
174
DQ60
37
A4
83
DQ56
129
DM3/DQS12
175
DQ61
38
VDD
84
DQ57
130
A3
176
VSS
39
DQ26
85
VDD
131
DQ30
177
DM7/DQS16
40
DQ27
86
DQS7
132
VSS
178
DQ62
41
A2
87
DQS8
133
DQ31
179
DQ63
42
VSS
88
DQ59
134
NC / CB4
180
VDDQ
43
A1
89
VSS
135
NC / CB5
181
SA0
44
NC / CB0
90
NC
136
VDDQ
182
SA1
45
NC / CB1
91
SDA
137
CK0
183
SA2
46
VDD
92
SCL
138
CK0
184
VDDSPD
47
NC / DQS8
139
VSS
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC ("no-connects") on x64 organised non-ECC
modules
HYS64/72D32000GU / HYS64/72D64020GU
Unbuffered DDR-I SDRAM-Modules
INFINEON Technologies
5
2.01
Block Diagram: One Bank 32M
64 DDR-I SDRAM DIMM Module
HYS64D32000GU using x8 organized SDRAMs on Raw Card Version B
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DM
I/O 7
I/O 6
I/O 1
I/O 0
D0
DM0/DQS9
I/O 5
I/O 4
I/O 3
I/O 2
DQ12
DQ13
DQ14
DQ8
DQ9
DQ10
DQ1 1
DM
I/O 7
I/O 6
I/O 1
I/O 0
D1
I/O 5
I/O 4
I/O 3
DM1/DQS10
DQ20
DQ21
DQ22
DQ23
DQ16
DQ17
DQ18
DQ19
DM
I/O 7
I/O 6
I/O 1
I/O 0
D2
I/O 5
I/O 4
I/O 3
I/O 2
DM2/DQS11
DQ28
DQ29
DQ30
DQ31
DQ24
DQ25
DQ26
DQ27
DM
I/O 7
I/O 6
I/O 1
I/O 0
D3
I/O 5
I/O 4
I/O 3
I/O 2
DM3/DQS12
DQ36
DQ37
DQ38
DQ39
DQ32
DQ33
DQ34
DQ35
DM
I/O 7
I/O 6
I/O 1
I/O 0
D4
DM4/DQS13
I/O 5
I/O 4
I/O 3
I/O 2
DQ44
DQ45
DQ46
DQ47
DQ40
DQ41
DQ42
DQ43
DM
I/O 7
I/O 6
I/O 1
I/O 0
D5
I/O 5
I/O 4
I/O 3
I/O 2
DM5/DQS14
DQ52
DQ53
DQ54
DQ55
DQ48
DQ49
DQ50
DQ51
DM
I/O 7
I/O 6
I/O 1
I/O 0
D6
I/O 5
I/O 4
I/O 3
I/O 2
DQ60
DQ61
DQ62
DQ63
DQ56
DQ57
DQ58
DQ59
DM
I/O 7
I/O 6
I/O 1
I/O 0
D7
I/O 5
I/O 4
I/O 3
I/O 2
DM7/DQS16
A0 - A12
A0 - A12: SDRAMs D0 - D7
A0
Serial PD
A1
A2
SA0
SA1
SA2
SCL
SDA
RAS
RAS : SDRAMs D0 - D7
CAS
CAS : SDRAMs D0 - D7
CKE0
CKE: SDRAMs D0 - D7
WE
WE : SDRAMs D0 - D7
S0
S
S
S
S
S
S
S
S
BA0 - BA1
BA0, BA1: SDRAMs D0 - D7
DQS0
DQS
DQS4
DQS1
DQS5
DQS
DQS2
DQS
DQS3
DQS
DM6/DQS15
DQS6
DQS7
DQ15
I/O 2
DQS
DQS
DQS
DQS
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
* Clock Wiring
*CK0/CK0
Clock
Input
SDRAMs
*CK1/CK1
2 SDRAMs
3 SDRAMs
3 SDRAMs
* Wire per Clock Loading
Table/Wiring Diagrams
*CK2/CK2
V
DD,
V
SS
V
DDQ
VREF
V
DDID
D0 - D7
D0 - D7
D0 - D7
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