82562G 10/100 Mbps Platform LAN
Connect (PLC)
Networking Silicon
Datasheet
Product Features
1
This device is lead-free. That is, lead has not been intentionally added, but lead may still exist
as an impurity at <1000 ppm. The Material Declaration Data Sheet, which includes lead
impurity levels and the concentration of other Restriction on Hazardous Substances (RoHS)-
banned materials, is available at:
ftp://download.intel.com/design/packtech/material_content_IC_Package.pdf#pagemode=bookmarks
In addition, this device has been tested and conforms to the same parametric specifications as
previous versions of the device.
For more information regarding lead-free products from Intel Corporation, contact your Intel
Field Sales representative.
Additional Features
The 82562G PLC supports drop-in replacement with the 82562ET. If it is not used as a drop-
in replacement, strapping options enable new operating modes:
--LED support for three logic configurations.
--LAN disable function using one pin.
--Increased transmit strength.
The receive BER performance increases the margin for cable length.
Return Loss performance is improved.
IEEE 802.3 10BASE-T/100BASE-TX
compliant physical layer interface
IEEE 802.3u Auto-Negotiation support
Digital Adaptive Equalization control
Link status interrupt capability
XOR tree mode support
3-port LED support (speed, link and
activity)
10BASE-T auto-polarity correction
LAN Connect Interface
Diagnostic loopback mode
1:1 transmit transformer ratio support
Low power (less than 300 mW in active
transmit mode)
Reduced power in "unplugged mode" (less
than 50 mW)
Automatic detection of "unplugged mode"
3.3 V device
Lead-free
1
48-pin Shrink Small Outline
Package for both leaded and lead-free
designs. (Devices that are lead-free are
marked with a circled "e3" and have the
product code prefix: LUxxxxxx).
Revision 1.3
April 2005
Datasheet
Revision History
Revision
Revision Date
Description
1.0
October 2004
Initial release (confidential status).
1.1
November 2004
Updated lead-free device information.
Updated Table 1 and Table 2 to reflect correct hardware configurations
and LED logic functionality.
Corrected signal names to match design guide and reference schemat-
ics.
1.2
January 2005
Added a note for PHY signals RBIAS100 and RBIAS10 to Section 4.3.
1.3
April 2005
Added internal/external pull-up/pull-down resistor values to the Hardware
Configuration table and signal definition tables for TESTEN,
ISOL_EXEC, ISOL_TI, ISOL_TCK, and ADV10/LAN_DISABLE#
Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no
liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are
not intended for use in medical, life saving, or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The 82562G PLC may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current
characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-
548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright 2005, Intel Corporation
* Other brands and names are the property of their respective owners.
Datasheet
i
82562G -- Networking Silicon
Contents
1.0
Introduction.........................................................................................................................1
1.1
Overview ......................................................................................................................1
1.2
References...................................................................................................................1
1.3
Product Codes .............................................................................................................1
2.0
82562G Architectural Overview..........................................................................................3
2.1
LAN Connect Interface.................................................................................................3
2.1.1
Reset/Synchronize Operations ..............................................................................4
2.1.2
Reset Considerations ............................................................................................4
2.1.3
LAN Connect Clock Operations.............................................................................5
2.2
Hardware Configuration ...............................................................................................5
3.0
Performance Enhancements..............................................................................................7
3.1
New Usage Modes: 1, 2, 3, and 4................................................................................7
3.1.1
Pin Usage for Modes 1, 2, 3, and 4 .......................................................................7
3.1.2
Enhanced Tx Mode................................................................................................8
4.0
82562G Signal Descriptions...............................................................................................9
4.1
Signal Type Definitions ...............................................................................................9
4.2
Twisted Pair Ethernet (TPE) Pins ...............................................................................9
4.3
External Bias Pins .......................................................................................................9
4.4
Clock Pins .................................................................................................................10
4.5
Platform LAN Connect Interface Pins .......................................................................10
4.6
LED Pins ...................................................................................................................11
4.7
Miscellaneous Control Pins .......................................................................................11
4.8
Power and Ground Connections ...............................................................................12
5.0
Physical Layer Interface Functionality..............................................................................13
5.1
100BASE-TX Mode....................................................................................................13
5.1.1
100BASE-TX Transmit Blocks.............................................................................13
5.1.2
100BASE-TX Receive Blocks..............................................................................15
5.2
10BASE-T Mode ........................................................................................................16
5.2.1
10BASE-T Transmit Blocks .................................................................................16
5.2.2
10BASE-T Receive Blocks ..................................................................................16
5.3
Analog References.....................................................................................................17
5.4
Dynamic Reduced Power & Auto Plugging Detection................................................17
5.4.1
Auto Plugging Detection ......................................................................................18
5.4.2
Dynamic Reduced Power ....................................................................................18
5.4.3
Configuration .......................................................................................................18
6.0
Platform LAN Connect Registers .....................................................................................19
6.1
Medium Dependent Interface (MDI) Registers 0 through 7 .......................................19
6.1.1
Register 0: Control Register Bit Definitions ........................................................19
6.1.2
Register 1: Status Register Bit Definitions ..........................................................20
6.1.3
Register 2: PHY Identifier Register Bit Definitions ..............................................21
6.1.4
Register 3: PHY Identifier Register Bit Definitions ..............................................21
6.1.5
Register 4: Auto-Negotiation Advertisement Register Bit Definitions .................21
ii
Datasheet
82562G -- Networking Silicon
6.1.6
Register 5: Auto-Negotiation Link Partner Ability Register Bit Definitions .......... 22
6.1.7
Register 6: Auto-Negotiation Expansion Register Bit Definitions ....................... 22
6.2
MDI Registers 8 through 15 ....................................................................................... 23
6.3
MDI Registers 16 through 31 ..................................................................................... 23
6.3.1
Register 16: PHY Status and Control Register Bit Definitions ............................ 23
6.3.2
Register 17: PHY Unit Special Control Bit Definitions ........................................ 24
6.3.3
Register 18: Reserved ........................................................................................ 24
6.3.4
Register 19: 100BASE-TX Receive False Carrier Counter Bit Definitions ......... 25
6.3.5
Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions ............ 25
6.3.6
Register 21: 100BASE-TX Receive Error Frame Counter Bit Definitions ........... 25
6.3.7
Register 22: Receive Symbol Error Counter Bit Definitions ............................... 25
6.3.8
Register 23: 100BASE-TX Receive Premature End of Frame
Error Counter Bit Definitions ............................................................................... 25
6.3.9
Register 24: 10BASE-T Receive End of Frame Error Counter Bit Definitions .... 26
6.3.10
Register 25: 10BASE-T Transmit Jabber Detect Counter Bit Definitions ........... 26
6.3.11
Register 27: PHY Unit Special Control Bit Definitions ........................................ 27
7.0
82562G Test Port Functionality........................................................................................ 29
7.1
Asynchronous Test Mode .......................................................................................... 29
7.2
Test Function Description .......................................................................................... 29
8.0
Electrical and Timing Specifications................................................................................. 31
8.1
Absolute Maximum Ratings ....................................................................................... 31
8.2
DC Characteristics .................................................................................................... 31
8.2.1
X1 Clock DC Specifications ................................................................................ 31
8.2.2
LAN Connect Interface DC Specifications .......................................................... 32
8.2.3
LED DC Specifications ....................................................................................... 32
8.2.4
10BASE-T Voltage and Current DC Specifications ............................................ 32
8.2.5
100BASE-TX Voltage and Current DC Specifications ........................................ 33
8.3
AC Characteristics ..................................................................................................... 34
8.3.1
10BASE-T Normal Link Pulse (NLP) Timing Parameters ................................... 34
8.3.2
Auto-Negotiation Fast Link Pulse (FLP) Timing Parameters .............................. 35
8.3.3
100BASE-TX Transmitter AC Specifications ...................................................... 36
8.3.4
Reset (RSTSYNC) AC Specifications ................................................................ 36
9.0
Package and Pinout Information ...................................................................................... 37
9.1
Package Information .................................................................................................. 37
9.2
Pinout Information...................................................................................................... 38
9.2.1
82562G Pin Assignments ................................................................................... 38
9.2.2
82562G Shrink Small Outline Package Diagram ................................................ 39
Networking Silicon -- 82562G
Datasheet
1
1.0
Introduction
This document is applicable to the Intel
82562G 10/100 Mbps Platform LAN Connect device, a
member of the 82562G Fast Ethernet device family.
1.1
Overview
The Intel
82562G 10/100 Mbps Platform LAN Connect is a highly-integrated device designed for
10 or 100 Mbps Ethernet systems. It is based on the IEEE 10BASE-T and 100BASE-TX standards.
The IEEE 802.3u standard for 100BASE-TX defines networking over two pairs of Category 5
unshielded twisted pair cable or Type 1 shielded twisted pair cable.
The 82562G complies with the IEEE 802.3u Auto-Negotiation standard and the IEEE 802.3x Full
Duplex Flow Control standard. The 82562G also includes a PHY interface compliant to the current
platform LAN connect interface.
1.2
References
IEEE 802.3 Standard for Local and Metropolitan Area Networks, Institute of Electrical and
Electronics Engineers.
82562ET(EM) and 82562GT(G) LAN on Motherboard Design Guide. Intel Corporation.
Intel
I/O Controller Hub 6 (ICH6) Family External Design Specification (EDS), Volume 1,
Revision 1.5V1. Intel Corporation.
Intel
I/O Controller Hub 6 (ICH6) Family External Design Specification (EDS), Volume 2,
Revision 1.5V2. Intel Corporation.
LAN Connect Interface Specification. Intel Corporation.
I/O Control Hub 2, 3, and 4 EEPROM Map and Programming Information. Intel Corporation.
I/O Control Hub 5, 6, and 7 EEPROM Map and Programming Information. Intel Corporation.
Programming information can be obtained through your local Intel representatives.
1.3
Product Codes
The product ordering code for the 82562G is: EP82562G.
The product ordering code for the 82562G lead-free version is: LU82562G.
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