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October 1995
COPYRIGHT
INTEL CORPORATION 1996
Order Number 290218-006
82596CA
HIGH-PERFORMANCE 32-BIT LOCAL
AREA NETWORK COPROCESSOR
Y
Performs Complete CSMA CD Medium
Access Control (MAC) Functions
Independently of CPU
IEEE 802 3 (EOC) Frame Delimiting
Y
Supports Industry Standard LANs
IEEE TYPE 10BASE-T
IEEE TYPE 10BASE5 (Ethernet )
IEEE TYPE 10BASE2 (Cheapernet)
IEEE TYPE 1BASE5 (StarLAN)
and the Proposed Standard
10BASE-F
Proprietary CSMA CD Networks Up
to 20 Mb s
Y
On-Chip Memory Management
Automatic Buffer Chaining
Buffer Reclamation after Receipt of
Bad Frames Optional Save Bad
Frames
32-Bit Segmented or Linear (Flat)
Memory Addressing Formats
Y
Network Management and Diagnostics
Monitor Mode
32-Bit Statistical Counters
Y
82586 Software Compatible
Y
Self-Test Diagnostics
Y
Optimized CPU Interface
Optimized Bus Interface to Intel's
i486
TM
DX i486
TM
SX i487
TM
SX and
80960CA Processors
33 MHz 25 MHz 20 MHz and 16 MHz
Clock Frequencies
Supports Big Endian and Little
Endian Byte Ordering
Y
32-Bit Bus Master Interface
106 MB s Bus Bandwidth
Burst Bus Transfers
Bus Throttle Timers
Transfers Data at 100% of Serial
Bandwidth
128-Byte Receive FIFO 64-Byte
Transmit FIFO
Y
Configurable Initialization Root for Data
Structures
Y
High-Speed 5V CHMOS
IV
Technology
Y
132-Pin Plastic Quad Flat Pack (PQFP)
and PGA Package
(See Packaging Spec Order No 240800-001
Package Type KU and A)
i486 is a trademark of Intel Corporation
Ethernet is a registered trademark of Xerox Corporation
CHMOS is a patented process of Intel Corporation
290218 1
Figure 1 82596CA Block Diagram
82596CA
82596CA High-Performance 32-Bit
Local Area Network Coprocessor
CONTENTS
PAGE
INTRODUCTION
3
PIN DESCRIPTIONS
7
82596 AND HOST CPU
INTERACTION
11
82596 BUS INTERFACE
11
82596 MEMORY ADDRESSING
11
82596 SYSTEM MEMORY
STRUCTURE
13
TRANSMIT AND RECEIVE MEMORY
STRUCTURES
14
TRANSMITTING FRAMES
17
RECEIVING FRAMES
18
82596 NETWORK MANAGEMENT AND
DIAGNOSTICS
18
NETWORK PLANNING AND
MAINTENANCE
20
STATION DIAGNOSTICS AND SELF-
TEST
21
82586 SOFTWARE COMPATIBILITY
21
INITIALIZING THE 82596
21
SYSTEM CONFIGURATION POINTER
(SCP)
21
Writing the Sysbus
22
INTERMEDIATE SYSTEM
CONFIGURATION POINTER
(ISCP)
23
INITIALIZATION PROCESS
23
CONTROLLING THE 82596CA
24
82596 CPU ACCESS INTERFACE
(PORT)
24
MEMORY ADDRESSING FORMATS
24
LITTLE ENDIAN AND BIG ENDIAN
BYTE ORDERING
25
COMMAND UNIT (CU)
26
RECEIVE UNIT (RU)
26
CONTENTS
PAGE
SYSTEM CONTROL BLOCK (SCB)
27
SCB OFFSET ADDRESSES
30
CBL Offset (Address)
30
RFA Offset (Address)
30
SCB STATISTICAL COUNTERS
31
Statistical Counter Operation
31
ACTION COMMANDS AND
OPERATING MODES
32
NOP
33
Individual Address Setup
33
Configure
34
Multicast-Setup
40
Transmit
41
Jamming Rules
43
TDR
44
Dump
46
Diagnose
49
RECEIVE FRAME DESCRIPTOR
50
Simplified Memory Structure
50
Flexible Memory Structure
51
Receive Buffer Descriptor (RBD)
52
PGA PACKAGE THERMAL
SPECIFICATIONS
57
ELECTRICAL AND TIMING
CHARACTERISTICS
57
Absolute Maximum Ratings
57
DC Characteristics
57
AC Characteristics
58
82596CA C-Step Input Output System
Timings
58
Transmit Receive Clock Parameters
63
82596CA BUS Operation
66
System Interface AC Timing
Characteristics
67
Input Waveforms
68
Serial AC Timing Characteristics
70
OUTLINE DIAGRAMS
72
REVISION HISTORY
76
2
82596CA
INTRODUCTION
The 82596CA is an intelligent high-performance
32-bit
Local
Area
Network
coprocessor
The
82596CA implements the CSMA CD access method
and can be configured to support all existing IEEE
802 3 standards
TYPEs 10BASE-T
10BASE5
10BASE2 1BASE5 and 10BROAD36 It can also be
used to implement the proposed standard TYPE
10BASE-F The 82596CA performs high-level com-
mands command chaining and interprocessor com-
munications via shared memory thus relieving the
host CPU of many tasks associated with network
control All time-critical functions are performed in-
dependently of the CPU this increases network per-
formance and efficiency The 82596CA bus interface
is
optimized
for
Intel's
i486
TM
SX
i486
TM
DX
i487
TM
SX 80960CA and 80960KB processors
The 82596CA implements all IEEE 802 3 Medium
Access Control and channel interface functions
these include framing
preamble generation and
stripping source address generation destination ad-
dress checking short-frame detection and automat-
ic length-field handling Data rates up to 20 Mb s are
supported
The 82596CA provides a powerful host system inter-
face It manages memory structures automatically
with command chaining and bidirectional data chain-
ing An on-chip DMA controller manages four chan-
nels this allows autonomous transfer of data blocks
(buffers and frames) and relieves the CPU of byte
transfer overhead Buffers containing errored or col-
lided frames can be automatically recovered without
CPU intervention The 82596CA provides an up-
grade path for existing 82586 software drivers by
providing an 82586-software-compatible mode that
supports the current 82586 memory structure The
82586CA also has a Flexible memory structure and
a Simplified memory structure The 82596CA can
address up to 4 gigabytes of memory The 82596CA
supports Little Endian and Big Endian byte ordering
The 82596CA bus interface can achieve a burst
transfer rate of 106 MB s at 33 MHz The bus inter-
face employs bus throttle timers to regulate
82596CA bus use Two large independent FIFOs
128 bytes for Receive and 64 bytes for Transmit
tolerate long bus latencies and provide programma-
ble thresholds that allow the user to optimize bus
overhead for any worst-case bus latency The high-
performance bus is capable of back-to-back trans-
mission and reception during the IEEE 802 3 9 6-ms
Interframe Spacing (IFS) period
The 82596CA provides a wide range of diagnostics
and network management functions these include
internal and external loopback exception condition
tallies channel activity indicators optional capture
of all frames regardless of destination address
(promiscuous mode) optional capture of errored or
collided frames and time domain reflectometry for
locating fault points on the network cable The sta-
tistical counters in 32-bit segmented and linear
modes are 32-bits each and include CRC errors
alignment errors overrun errors resource errors
short frames and received collisions The 82596CA
also features a monitor mode for network analysis
In this mode the 82596CA can capture status bytes
and update statistical counters of frames monitored
on the link without transferring the contents of the
frames to memory This can be done concurrently
while transmitting and receiving frames destined for
that station
The 82596CA can be used in both baseband and
broadband networks It can be configured for maxi-
mum network efficiency (minimum contention over-
head) with networks of any length Its highly flexible
CSMA CD unit supports address field lengths of
zero through six bytes for IEEE 802 3 Ethernet
frame delimitation It also supports 16- or 32-bit cy-
clic redundancy checks The CRC can be trans-
ferred directly to memory for receive operations or
dynamically inserted for transmit operations The
CSMA CD unit can also be configured for full duplex
operation for high throughput in point-to-point con-
nections
The 82596 C-step incorporates several new features
not found in previous steppings The following is a
summary of the 82596 C-step's new features
The 82596 C-step fixes Errata found in the A1
and B steppings
The 82596 C-step has improved AC timings over
both the A and B steppings
The 82596 C-step has a New Enhanced Big Endi-
an Mode where in Linear Addressing Mode true
32-bit Big Endian functionality is achieved New
Enhanced Big Endian Mode is enabled by setting
bit 7 of the SYSBUS byte This mode is software
compatible with the big endian mode of the
B-step with one exception
no 32-bit addresses
need to be swapped by software in the C-step In
this new mode the 82596 C-step treats 32-bit ad-
dress pointers as true 32-bit entities and the SCB
absolute address and statistical counters are still
treated as two 16-bit big endian entities Not set-
ting this mode will configure the 82596 C-step to
be 100% compatible to the A1-step big endian
mode
The 82596 C-step is hardware and software com-
patible to both the A1 and B steppings allowing
for easy ``drop-in'' to current designs Pinout and
control structures remain unchanged
3
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