TECHNICAL
BRIEF
i960
RP Processor: A Single-Chip
Intelligent I/O Subsystem
i960
RP MICROPROCESSOR TECHNICAL BRIEF
ii
Information in this document is provided solely to enable use of Intel products. Intel assumes no liability whatsoever, including infringement of any
patent or copyright, for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products.
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document
nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order.
MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation.
Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark or products.
*Other brands and names are the property of their respective owners.
Additional copies of this document or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
or call 1 (800) 548-4725
INTEL CORPORATION 1995
iii
TABLE OF CONTENTS
INTRODUCTION .............................................................................................................................................. 1
Examples of Intelligent I/O Innovation............................................................................................................ 1
Storage I/O Interfaces ................................................................................................................................... 2
Network I/O Interfaces .................................................................................................................................. 2
Emerging Technologies ................................................................................................................................. 3
Expanding the Market for Intelligent I/O by Reducing System Costs .............................................................. 3
Expanding Server Capabilities with an Intelligent I/O Subsystem ................................................................... 3
Intelligent I/O Processor Requirements ......................................................................................................... 4
i960
RP PROCESSOR TECHNICAL OVERVIEW ........................................................................................... 1
i960
RP PROCESSOR HIGHLIGHTS ............................................................................................................. 1
Core Architecture Performance ..................................................................................................................... 0
Fast Call-and-Return Mechanism .................................................................................................................. 0
Set-Associative Cache Design....................................................................................................................... 1
Enhanced Bus Control Unit ........................................................................................................................... 1
Superior Interrupt Performance ..................................................................................................................... 1
i960
RP Processor Integrated Peripherals .................................................................................................... 0
i960
RP PROCESSOR DATA FLOW REQUIREMENTS ................................................................................. 0
PCI-TO-PCI BRIDGE ....................................................................................................................................... 0
Electrically Isolated PCI Buses ...................................................................................................................... 0
Isolated Data Flow ........................................................................................................................................ 0
i960
RP Processor Bridge Address Decode .................................................................................................. 0
ISA Address Forwarding................................................................................................................................ 0
VGA Addressing and Snooping Support ........................................................................................................ 20
VGA-Compatible Addressing ......................................................................................................................... 0
64-Bit Addressing with Dual Address Cycle ................................................................................................... 0
Bridge Queues .............................................................................................................................................. 2
PCI Bridge Transactions................................................................................................................................ 2
PCI Data Streaming ...................................................................................................................................... 1
ADDRESS TRANSLATION UNITS (ATU)......................................................................................................... 1
ATU Queues ................................................................................................................................................. 2
ATU Inbound Transactions ............................................................................................................................ 2
Inbound ATU Data Streaming........................................................................................................................ 2
Outbound ATU Transactions ......................................................................................................................... 2
ATU Direct Addressing Transactions ............................................................................................................. 3
Generating PCI Configuration Cycles ............................................................................................................ 3
5
7
7
8
10
11
12
13
14
14
14
14
16
16
17
17
19
19
20
21
23
23
23
23
24
24
6
i960
RP MICROPROCESSOR TECHNICAL BRIEF
iv
PRIVATE PCI DEVICES................................................................................................................................... 3
Private PCI Address Space ........................................................................................................................... 0
MESSAGING UNIT .......................................................................................................................................... 2
Message Registers........................................................................................................................................ 2
Doorbell Registers......................................................................................................................................... 2
Circular Queues ............................................................................................................................................ 2
Index Registers ............................................................................................................................................. 2
DMA CONTROLLER ........................................................................................................................................ 2
Hardware Unaligned DMA Transfers ............................................................................................................. 0
DMA Chaining Operation............................................................................................................................... 0
DMA Channel Queues................................................................................................................................... 1
DMA Transactions......................................................................................................................................... 2
Demand Mode DMA Transfers ...................................................................................................................... 37
BUS ARBITRATION SUPPORT ....................................................................................................................... 2
Local Bus Arbitration Unit .............................................................................................................................. 0
Secondary PCI Bus Arbitration Unit ............................................................................................................... 1
Primary and Secondary Internal PCI Bus Arbiters.......................................................................................... 1
INTEGRATED MEMORY CONTROLLER......................................................................................................... 1
DRAM Control ............................................................................................................................................... 0
Programmable Refresh Timer ....................................................................................................................... 0
DRAM Performance ...................................................................................................................................... 0
Memory Controller Error Reporting ................................................................................................................ 0
Programmable Byte Parity for DRAM ............................................................................................................ 0
Bus Monitor Support...................................................................................................................................... 0
SRAM, Flash and ROM Control..................................................................................................................... 0
FILTERING PCI INTERRUPTS ........................................................................................................................ 2
I/O APIC Interface......................................................................................................................................... 0
SERIAL I
2
C INTERFACE .................................................................................................................................. 0
i960
RP PROCESSOR CLOCKING................................................................................................................. 1
PCI Configuration .......................................................................................................................................... 0
Peripheral Programming Interface ................................................................................................................. 0
Reset Configuration Options.......................................................................................................................... 1
i960
RP PROCESSOR PACKAGING .............................................................................................................. 1
COMPLETE TOOL SET FOR EMBEDDED DESIGN........................................................................................ 0
State-of-the-Art Compiler Technology............................................................................................................ 0
Integrated Software Debuggers .....................................................................................................................
30
32
32
33
33
34
34
36
36
36
38
39
39
39
39
42
42
44
45
45
45
46
47
48
48
48
27
27
27
29
30
30
31
25
25
27
v
Wide Variety of Operating Systems ............................................................................................................... 0
Emulators and Logic Analyzers ..................................................................................................................... 0
Evaluation Platforms ..................................................................................................................................... 0
i960
Microprocessor PCI I/O Software Development Kit ............................................................................... 1
PCI Compliance ............................................................................................................................................ 1
SUMMARY ....................................................................................................................................................... 0
48
48
48
49
49
49
PDF 
ZIP