4-1

File Number

4718.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-724-7143

Intersil Corporation 1999

HI5905N/QML

14-Bit, 5 MSPS, Military A/D Converter

The HI5905N/QML is a monolithic, 14-bit, 5MSPS Analog-
to-Digital Converter fabricated in an advanced BiCMOS
process. It is designed for high speed, high resolution
applications where wide bandwidth, low power consumption
and excellent SINAD performance are essential. With a
100MHz full power input bandwidth and high frequency
accuracy, the converter is ideal for many Military types of
communication systems employing digital IF architectures.

The HI5905N/QML is designed in a fully differential pipelined
architecture with a front end differential-in-differential-out
sample-and-hold amplifier (S/H). Consuming 350mW (typ)
power at 5MSPS, the HI5905N/QML has excellent dynamic
performance over the full Military temperature range.

Data output latches are provided which present valid data to
the output bus with a data latency of only 4 clock cycles.

Specifications for QML devices are controlled by the
Defense Supply Center in Columbus (DSCC). The SMD
numbers listed below must be used when ordering.

Detailed Electrical Specifications for the HI5905N/QML
are contained in SMD 5962-98591. That document may
be easily downloaded from our website.
http://www.Intersil.com/data/sm/index.htm

Pinout

HI5905 (MQFP) (MO-108AA-2 ISSUE A)

TOP VIEW

Features

· QML Compliant per SMD 5962-9859101NXB

· Sampling Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . .5MSPS

· Low Power at 5MSPS. . . . . . . . . . . . . . . . . 400mW (Max)

· Internal Sample and Hold

· Fully Differential Architecture

· Full Power Input Bandwidth . . . . . . . . . . . . . . . . . 100MHz

· SINAD at 1MHz . . . . . . . . . . . . . . . . . . . . . . >69dB (Min)

· Internal Voltage Reference

· TTL Compatible Clock Input

· CMOS Compatible Digital Data Outputs

Applications

· Digital Communication Systems

· Undersampling Digital IF

· Asymmetric Digital Subscriber Line (ADSL)

· Document Scanners

· Reference Literature

- AN9214, Using Intersil High Speed A/D Converters

- AN9785, Using the Intersil HI5905 EVAL2 Evaluation

Board

12 13 14 15 16 17

39 38 37 36 35 34

44 43 42 41 40

GND

IN+

IN-

GND1

CC2

GND2

OUT

RIN

GND

D13

D12

D11

D10

CC1

GND1

CC1

CLK

Ordering Information

ORDERING

NUMBER

INTERNAL INTERSIL

MKT. NUMBER

TEMP.

RANGE(

5962-9859101NXB

HI5905N/QML

-55 to 125

HI5905EVAL2

Low Frequency Platform

Data Sheet

July 1999

4-2

Functional Block Diagram

Typical Application Schematic

BIAS

4-BIT

FLASH

4-BIT

DAC

4-BIT

FLASH

STAGE 5

STAGE 4

STAGE 1

GND

CC1

GND1

DIGIT

AL DELA

D13 (MSB)

D10

D0 (LSB)

4-BIT

FLASH

4-BIT

DAC

AND

DIGIT

AL ERR

OR CORRECTION

CLOCK

REF

CC2

GND2

ROUT

CLK

RIN

S/H

D12

D11

RIN

(14)

HI5905

ROUT

(13)

- (10)

CLK (40)

GND1

(42)

GND2

(26)

GND1

(3)

GND

(15)

(16) DV

CC2

(27)

D9 (24)

D8 (25)

D7 (29)

D6 (30)

D5 (31)

D4 (32)

D3 (33)

D2 (36)

D1 (37)

(LSB) D0 (38)

AS CLOSE TO PART AS POSSIBLE

F AND 0.1

F CAPS ARE PLACED

BNC

CLOCK

0.1

GND

(6)

+ (9)

GND

CC1

(41)

CC1

(43)

(11)

D10 (21)

D10

(MSB) D13 (18)

D11

(5)

+5V

D12

D13

D11 (20)

D12 (19)

4-3

Timing Waveforms

ANALOG

INPUT

CLOCK

INPUT

S/H

1ST

STAGE

2ND

STAGE

3RD

STAGE

4TH

STAGE

DATA

OUTPUT

N - 1

N + 1

N + 2

N + 3

N + 4

N + 5

N + 6

1, N + 5

1, N + 4

1, N + 3

1, N + 2

1, N + 1

1, N

N - 1

N - 2

N - 3

N - 4

N - 1

N - 2

N - 3

LAT

N - 2

N - 1

N + 1

N - 1

N + 1

N + 2

N + 3

N + 2

N + 1

N + 3

N + 4

N + 3

N + 2

5TH

STAGE

N - 3

N - 2

N - 1

N + 1

N + 2

N + 3

NOTES:

1. S

: N-th sampling period.

2. H

: N-th holding period.

3. B

M, N

: M-th stage digital output corresponding to N-th sampled input.

4. D

: Final data output corresponding to N-th sampled input.

FIGURE 1. INTERNAL CIRCUIT TIMING

DATA N-1

DATA N

CLOCK

INPUT

DATA

OUTPUT

1.5V

3.5V

1.5V

ANALOG

INPUT

1.5V

FIGURE 2. INPUT-TO-OUTPUT TIMING

4-4

Detailed Description

Theory of Operation

The HI5905 is a 14-bit fully differential sampling pipeline A/D
converter with digital error correction. Figure 3 depicts the
circuit for the front end differential-in-differential-out sample-
and-hold (S/H). The switches are controlled by an internal
clock which is a non-overlapping two phase signal,

and

, derived from the master clock. During the sampling

phase,

, the input signal is applied to the sampling

capacitors, C

. At the same time the holding capacitors, C

are discharged to analog ground. At the falling edge of

the input signal is sampled on the bottom plates of the
sampling capacitors. In the next clock phase,

, the two

bottom plates of the sampling capacitors are connected
together and the holding capacitors are switched to the op
amp output nodes. The charge then redistributes between
C

and C

completing one sample-and-hold cycle. The

output is a fully-differential, sampled-data representation of
the analog input. The circuit not only performs the sample-
and-hold function but will also convert a single-ended input
to a fully-differential output for the converter core. During the
sampling phase, the V

pins see only the on-resistance of a

switch and C

. The relatively small values of these

components result in a typical full power input bandwidth of
100MHz for the converter.

As illustrated in the functional block diagram and the timing
diagram in Figure 1, four identical pipeline subconverter
stages, each containing a four-bit flash converter, a four-bit
digital-to-analog converter and an amplifier with a voltage
gain of 8, follow the S/H circuit with the fifth stage being only
a 4-bit flash converter. Each converter stage in the pipeline
will be sampling in one phase and amplifying in the other
clock phase. Each individual sub-converter clock signal is
offset by 180 degrees from the previous stage clock signal,
with the result that alternate stages in the pipeline will
perform the same operation.

The output of each of the four-bit subconverter stages is a
four-bit digital word containing a supplementary bit to be
used by the digital error correction logic. The output of each
subconverter stage is input to a digital delay line which is
controlled by the internal sampling clock. The function of the
digital delay line is to time align the digital outputs of the four

Pin Descriptions

PIN #

NAME

DESCRIPTION

No Connection

GND1

Digital Ground

No Connection

Analog Supply (5.0V)

GND

Analog Ground

No Connection

Positive Analog Input

Negative Analog Input

DC Bias Voltage Output

No Connection

ROUT

Reference Voltage Output

RIN

Reference Voltage Input

GND

Analog Ground

Analog Supply (5.0V)

No Connection

D13

Data Bit 11 Output (MSB)

D12

Data Bit 11 Output

D11

Data Bit 11 Output

D10

Data Bit 10 Output

No Connection

Data Bit 9 Output

Data Bit 8 Output

GND2

Digital Ground

CC2

Digital Supply (5.0V)

No Connection

Data Bit 7 Output

Data Bit 6 Output

Data Bit 5 Output

Data Bit 4 Output

Data Bit 3 Output

No Connection

Data Bit 2 Output

Data Bit 1 Output

Data Bit 0 Output (LSB)

No Connection

CLK

Input Clock

CC1

Digital Supply (5.0V)

GND1

Digital Ground

CC1

Digital Supply (5.0V)

No Connection

OUT

FIGURE 3. ANALOG INPUT SAMPLE-AND-HOLD

4-5

identical four-bit subconverter stages with the corresponding
output of the fifth stage flash converter before applying the
twenty bit result to the digital error correction logic. The
digital error correction logic uses the supplementary bits to
correct any error that may exist before generating the final
fourteen bit digital data output of the converter.

Because of the pipeline nature of this converter, the digital
data representing an analog input sample is output to the
digital data bus on the 4th cycle of the clock after the analog
sample is taken. This time delay is specified as the data
latency. After the data latency time, the digital data
representing each succeeding analog sample is output
during the following clock cycle. The digital output data is
synchronized to the external sampling clock with a latch. The
digital output data is available in two's complement binary
format (see Table 1, A/D Code Table).

Internal Reference Generator, V

ROUT

and V

RIN

The HI5905 has an internal reference generator, therefore, no
external reference voltage is required. V

ROUT

must be

connected to V

RIN

when using the internal reference voltage.

The HI5905 can be used with an external reference. The
converter requires only one external reference voltage
connected to the V

RIN

pin with V

ROUT

left open.

The HI5905 is tested with V

ROUT

, equal to 4.0V, connected

to V

RIN

. Internal to the converter, two reference voltages of

1.3V and 3.3V are generated for a fully differential input
signal range of

2V.

In order to minimize overall converter noise, it is
recommended that adequate high frequency decoupling be
provided at the reference voltage input pin, V

RIN

Analog Input, Differential Connection

The analog input to the HI5905 can be configured in various
ways depending on the signal source and the required level
of performance. A fully differential connection (Figure 4) will
give the best performance for the converter.

Since the HI5905 is powered off a single +5V supply, the
analog input must be biased so it lies within the analog input

common mode voltage range of 1.0V to 4.0V. The
performance of the ADC does not change significantly with
the value of the analog input common mode voltage.

A 2.3V DC bias voltage source, V

, half way between the

top and bottom internal reference voltages, is made
available to the user to help simplify circuit design when
using a differential input. This low output impedance voltage
source is not designed to be a reference but makes an
excellent bias source and stays within the analog input
common mode voltage range over temperature.

The difference between the converter's two internal voltage
references is 2V. For the AC coupled differential input, (Figure
4), if V

is a 2V

P-P

sinewave with -V

being 180 degrees out of

phase with V

, then V

+ is a 2V

P-P

sinewave riding on a DC

bias voltage equal to V

and V

- is a 2V

P-P

sinewave riding

on a DC bias voltage equal to V

. Consequently, the converter

will be at positive full scale, resulting in a digital data output code
with D13 (MSB) equal to a logic "0" and D0-D12 equal to logic
"1" (see Table 1, A/D Code Table), when the V

+ input is at

+1V and the V

- input is at VDC-1V (V

+ - V

- = 2V).

Conversely, the ADC will be at negative full scale, resulting in a
digital data output code with D13 (MSB) equal to a logic "1" and
D0-D12 equal to logic "0" (see Table 1, A/D Code Table), when
the V

+ input is equal to V

-1V and V

- is at V

+1V

+-V

- = -2V). From this, the converter is seen to have a

peak-to-peak differential analog input voltage range of 2V.

The analog input can be DC coupled (Figure 5) as long as
the inputs are within the analog input common mode voltage
range (1.0V

VDC

4.0V).

HI5905

-V

FIGURE 4. AC COUPLED DIFFERENTIAL INPUT

TABLE 1. A/D CODE TABLE

CODE

CENTER

DESCRIPTION

DIFFERENTIAL

INPUT VOLTAGE

(USING INTERNAL

REFERENCE)

TWO'S COMPLEMENT BINARY OUTPUT CODE

MSB

LSB

D13

D12

D11

D10

+Full Scale
(+FS) - 1/4 LSB

+1.99994V

+FS

1 1/4 LSB

1.99969V

+ 3/4 LSB

183.105

- 1/4 LSB

-61.035

-FS + 1 3/4 LSB

-1.99957V

-Full Scale
(-FS) + 3/4 LSB

-1.99982V

The voltages listed above represent the ideal center of each two's complement binary output code shown.

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